Hardware Interrupts
Hardware interrupts:

  • An external device initiates the hardware interrupts and placing an appropriate signal at the interrupt pin of the processor.

  • If the interrupt is accepted then the processor executes an interrupt service routine.

The 8085 has five hardware interrupts

(1) TRAP             (2) RST 7.5             (3) RST 6.5         (4) RST 5.5       (5) INTR




TRAP:
  • This interrupt is a non-maskable interrupt. It is unaffected by any mask or interrupt enable.

  • TRAP bas the highest priority and vectored interrupt.

  • TRAP interrupt is edge and level triggered. This means hat the TRAP must go high and remain high until it is acknowledged.

  • In sudden power failure, it executes a ISR and send the data from main memory to backup memory.

  • The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor receives HOLD and TRAP at the same time then HOLD is recognized first and then TRAP is recognized).

  • There are two ways to clear TRAP interrupt.

               1.By resetting microprocessor (External signal)
               2.By giving a high TRAP ACKNOWLEDGE (Internal signal)

RST 7.5:

  • The RST 7.5 interrupt is a maskable interrupt.

  • It has the second highest priority.

  • It is edge sensitive. ie. Input goes to high and no need to maintain high state until it recognized.

  • Maskable interrupt. It is disabled by,

               1.DI instruction
               2.System or processor reset.
               3.After reorganization of interrupt.

  • Enabled by EI instruction.



RST 6.5 and 5.5:

  • The RST 6.5 and RST 5.5 both are level triggered. . ie. Input goes to high and stay high until it recognized.

  • Maskable interrupt. It is disabled by,

               1.DI, SIM instruction
               2.System or processor reset.
               3.After reorganization of interrupt.

  • Enabled by EI instruction.

  • The RST 6.5 has the third priority whereas RST 5.5 has the fourth priority.

INTR:

  • INTR is a maskable interrupt. It is disabled by,

               1.DI, SIM instruction
               2.System or processor reset.
               3.After reorganization of interrupt.

  • Enabled by EI instruction.

  • Non- vectored interrupt. After receiving INTA (active low) signal, it has to supply the address of ISR.

  • It has lowest priority.

  • It is a level sensitive interrupts.  ie. Input goes to high and it is necessary to maintain high state until it recognized.

  • The following sequence of events occurs when INTR signal goes high.
1. The 8085 checks the status of INTR signal during execution of each instruction.

2. If INTR signal is high, then 8085 complete its current instruction and sends active low                interrupt acknowledge signal, if the interrupt is enabled.

3. In response to the acknowledge signal, external logic places an instruction OPCODE on the data bus. In the case of multibyte instruction, additional interrupt acknowledge machine cycles are generated by the 8085 to transfer the additional bytes into the microprocessor.

4. On receiving the instruction, the 8085 save the address of next instruction on stack and execute        received instruction.
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