I/O Interfacing methods of 8085 -Free 8085 Microprocessor lecture

Example 1:

A system requires 16kb EPROM and 16kb RAM. Also the system has 2 numbers of 8255, one number of 8279, one number of 8251 and one number of 8254. (8255 - Programmable peripheral interface; 8279-Keyboard/display controller, 8251 - USART and 8254 - Timer). Draw the Interface diagram. Allocate addresses to all the devices. The peripheral IC should be I/O mapped.

The I/O devices in the system should be mapped by standard I/O mapping. Hence separate decoders can be used to generate chip select signals for memory IC and peripheral IC's.
For 16kb EPROM, we can provide 2 numbers of 2764(8k x 8) EPROM.
For 16kb RAM we can provide 2 numbers of 6264 (8k x 8) RAM.
The 8kb memories require 13 address lines. Hence the address lines A0 - A12 are used for selecting the memory locations.
The unused address lines A13, A14 and A15 are used as input to decoder 74LS138 (3-to-8-deeoder) of memory IC. The logic low enables of this decoder are tied to IO/ M(low) of 8085, so that this decoder is enabled for memory read/write operation. The other enable pins of decoder are tied to appropriate logic levels permanently. The 4-outputs of the decoder are used to select memory lCs and the remaining 4 are kept for future expansion.
The EPROM is mapped in the beginning of memory space from 0000H to 3FFF.
The RAM is mapped at the end of memory space from C000 to FFFFH.
There are five peripheral IC's to be interfaced to the system. The chip-select signals for these IC's are given through another 3-to-8 decoder 74LS138 (I/O decoder). The input to this decoder is A11, A12 and A13
The address lines A13, A14 and A15 are logically ORed and applied to low enable of I/O decoder.
The logic high enable of I/O decoder is tied to IO / M(low) signal of 8085, so that this decoder is enabled for I/O read/write operation.