Counters, Registers, and State Machines
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We can now apply what we know about basic flip-flops circuit elements to develop new functions: counters and registers. In doing so, we will introduce the "state machine", a clocked sequential "processor".
Divide by Two Counter
The edge-triggered D-type flip-flops which we introduced in the previous Section are quite useful and versatile building blocks of sequential logic. A simple application is the divide-by-2 counter shown in Fig. 19, along with the corresponding timing diagram.
Figure 19: Positive edge-triggered D-type flip-flop connected as divide-by-2 counter.
Asynchronous Counter
Flip-flops can be connected in series, as shown in Fig. 21. The resulting outputs are given in Fig. 22. Hence, this is a 4-bit counter, with maximum count 24 - 1 = 15. It is clearly possible to expand such a counter to an indefinite number of bits.
While asynchronous counters are easy to assemble, they have serious drawbacks for some applications. In particular, the input must propogate through the entire chain of flip-flops before the correct result is achieved. Eventually, at high input rate, the two ends of the chain, representing the LSB and MSB, can be processing different input pulses entirely. (Perhaps in lab you can see this e ect on the oscilloscope with a very high input frequency.) The solution to this is the synchronous counter, which we will discuss below as an example of a state machine.
Figure 21: Asynchronous ("ripple") counter made from cascaded D-type flip-flops.
Figure 22: Waveforms generated by the ripple counter.
Registers
The figure below represents a 4-bit memory. We can think of it as 4 individual D-type flip-flops. The important point about a data register of this type is that all of the inputs are latched into memory synchronously by a single clock cycle.
Figure 23: 4-bit data register.
Shift Registers
The figure below is an example of a 4-bit shift register. These configurations are quite useful, particularly for transforming serial data to parallel, and parallel to serial. In the circuit below, a pulse appearing at \serial in" would be shifted from the output of one flip-flop to the next on each clock cycle. Hence a serial bit pattern at the input (4 bits long in this example) would appear as 4 parallel bits in the outputs Q0-Q3 after 4 clock cycles. This represents the serial-to-parallel case.
Figure 24: 4-bit shift register.
