Abstract :MB89P475 is produced eight Fujitsu MCU . The microcontroller has a wealth of software and hardware resources and good EMC performance, can be widely used in home appliance control products. The device includes two-way UART / SIO interface, very suitable for computer centralized control and management of multi-level communications control system. In this paper, the characteristics of the microcontroller and the UART / SIO structure type is given MB89P475 central air conditioning in LSP300 Computer Control System Design and Application Method . Keywords :MB89P475; SCM ; central air conditioning ; Computer Control System MB89P475 is a Fujitsu company's F2MC-8L MB89470 microcontroller series. The product has extensive software and hardware resources and good EMC performance program space (16k × 8bits PROM) and the data space (512 × 8bits RAM) moderate size , timer and interrupt resources, rich in resources. Dual UART / SIO interface setting is a major feature of the product . Design in order to use the 16-bit microcontroller can directly compare the data and arithmetic . MB89P475 cost-effective and rational allocation of resources, so that it can be widely used in household appliances control and industrial control applications. In addition, multi-stage development of data communication control system design , MB89P475 MCU is a rare product . 1 MB89P475 Introduction 1.1 Pin function MB89P475 (OTP type ) the appropriate mask (MASK) Model for the MB89475, which has two packages , namely, 48-pin Plastic SH-DIP and 48-pin Plastic QFP package . In this paper, SH-DIP package as an example to introduce the pin definitions , Figure 1 shows the package pinout diagram , now the pin function as follows: X0, X1: oscillator input, output ; MODE: mode setting pin , to use , the pin is usually connected directly to ground ; RST: Reset pin , active low reset ; P00/AN0 ~ P07/AN7: Universal I / O port or the A / D input ; P10 ~ P13: General I / O port or edge triggered interrupt input ; P14 ~ P17: General I / O port or timer input (EC), output (TO); P20 ~ P22: General I / O port or UART/SIO1 clock input , data output and input ; P23: General I / O port or a PWC ( pulse width measurement ) input ; P24: General I / O port or a PWM ( pulse width modulation) output ; P25 ~ P27: General I / O port or UART/SIO2 of data input , data output , clock input ; P30 * ~ P36 *: High current driver output , which , P30/BUZ * can be used for buzzer driving P40 ~ P41: In MB89P475 (102) ( single- clock system) for general input , the MB89P475 (202) ( two- clock system ), the vice- clock connection pin ; P42: General Input ; P50 ~ P54: General I / O port or level triggered interrupt input ( low interruption ); C: 0.1µF capacitor connected to ground ; Vcc, Vss: Power (+5 V) and ground (GND) pins ; Avcc, Avss: A / D circuit of the reference power supply and ground . 1.2 Features MB89P475 contains six timers , namely : PWC ( pulse width measurement) timer ( interval timer can be used ), PWM ( pulse width modulation ) timer ( interval timer can be used ), 2 8 / 16bit timer / counter, a 21-bit time base timer , and a ratio of device Watch . In addition , MB89P475 also has the following characteristics: ? with a buzzer driven by the program selection seven kinds of drive signal frequency ; ? can be external interrupt , including the edge triggered interrupt channels 4 and 5 level triggered interrupts channel; ? 8-channel embedded 10-bit A / D converter; Figure 3 RS-232/RS-485 converter circuit Click to enlarge ? includes UART / SIO asynchronous / synchronous data receiver / transmitter ; Emission data is written SODR1 / 2 registers , the emission data, while TDRE flag is cleared , " 0 " , launch the data transferred to the shift register after the launch , TDRE is set to "1" , which means SODR1 / 2 the next registers can be written Emission data, if the interruption to allow launch will have a launch interrupt request . ? Low power consumption can work with the Stop mode , Sleep mode , the Deputy clock mode , Watch mode and other operating modes ; ? Watchdog timer with reset function ; 39 Road ? maximum available I / O port . 2 MB89P475 the UART / SIO Structure MB89P475 internal integration is most characteristic of a UART / SIO universal serial data communication interface, can be achieved through the on-chip full-duplex double buffer at the same time two-way communication ? ? UART / SIO programmable configured for asynchronous or synchronous communication mode ; its internal Baud rate generator can choose 14 different baud rate ? external clock to set the baud rate may also be ? The data format in table 1. The data transmission format based on NRZ ( non return to zero ) system. (1) SMC11/21: Mode Control Register 1 ( Address : 0026H/002BH, initialization value : 00000000H) the following format: One , MD for the communication mode control bit , the bit is 0 for asynchronous communication (UART), synchronous communication is 1 (SIO); PEN as the check control bit , the bit is 0 for no parity, expressed as a checksum ( chosen by the Bit5 odd and even check ); TDP for the odd and even parity bit , 0 for even parity, one for the odd check ; SBL is the stop bit length of the control bits , 0 to select 1Bit stop bit , 1 stop bit for the selection of 2 Bit ; CL for the character length control bit , 0 for the selection of 7 Bit data length , a data length for the selection of 8 Bit ; CLK2 ~ CLK0: Communication Clock Select bits , see Table 2 lists the specific operation . Which , RERC: Clear the flag bit received . Set 0, remove all the error flag , set an invalid ; RXE: data reception allows bit , set against receiving 0 , set 1 allowed to receive ; TXE: data emission permit spaces ban fired home 0 , 1 set to allow emission; BRGE: start bit baud rate generator , 0 to stop , one for the start ; TXOE: serial data output enable bit , Chi 0 , P21/SO1, P26/SO2 a universal I / O port , set 1 , P21/SO1, P26/SO2 for the serial data output port ; SCKE: Serial clock output enable bit , Chi 0 , P20/SCK1, P27/SCK2 a universal I / O port or serial clock input , set 1 , P20/SCK1, P27/SCK2 for the serial clock output ; RIE: Receive Interrupt Enable bit set to 0 , the receiver suspended ban , set to 1 , the receive interrupt to allow ; TIE: launch break to allow bit set to 0 when the interrupt prohibiting launch , set 1, the launch of interruption allowed . (3) SSD1 / 2: Status and Data register (address : 0028H/002DH, initialization value :00001 --- H), the following format: Which , PRE: To check the error flag , 0 for no validation error , an error for the validation ; OVE: Overflow error flag , 0 for no overflow errors , 1 for overflow error ; FER: frame error flag , 0 for no frame error , an error for the frame ; RDRF: Receive data register full flag , 0 for the register air , 1 to receive data over ; TDRE: emission data register empty flag , 0 for the emission data is full, a space for the Here , SSD1 / 2 is read-only register . If the receive interrupt to allow (RIE = 1), then any error flag is set to "1" will have to receive interrupt . Therefore , the program will RERC (SMC12/22 in Bit7) set to "1" , the error flag can be cleared . (4) SRC1 / 2: Baud Rate Control Register (Address : 002AH/002FH, initialization value : xxxxxxxxH) When SMC11/SMC21 registers CLK2 ~ CLK0 set to " 011 " , because the baud rate generator is selected as the serial clock ( asynchronous mode only) , so only in UART / SIO to stop work, write SRC1 / 2 data to be effective. At this point, the baud rate is calculated as follows (CLK2 ~ CLK0 set to " 011 "): Baud rate = 1 / (16nTint) The formula , n is written SRC1 / 2 values , Tint for the instruction cycle , its value can be programmed by setting the relevant register as 4/fch, 8/fch, 16/fch, 64/fch ( including the system clock fch Oscillator frequency) . (5) SIDR1 / 2: input data register ( address : 0029H/002EH, initialization value : xxxxxxxxH) The register used to store the received data . When data reception is complete , RSRF bit (SSD1 / 2 in Bit4) is set to "1" , at this time if the receiver interrupt permission to receive interrupt requests . After receiving data read out , RSRF -bit auto- clear "0 . " System detects reception interrupt request , check the RSRF bit is "1" , if "0 "indicating that the failure was due to receive an error generated , SIDR1 / 2 did not receive the data , then the appropriate procedure should be In the corresponding treatment . (6) SODR1 / 2: output data register (address : 0029H/002EH, initialization value : xxxxxxxxH) SODR1 / 2 and SIDR1 / 2 has the same address. Emission permits, emission data will be written to the register can be directly transferred to the launch of registers , and through the launch of the shift register is sent to the serial data output (SO1 / 2). Figure 5 Click to enlarge If we launch the data length set to 7 Bits, the data section 7 ( highest ) is invalid. 3 LSR300 type composition of Control System Figure 2 shows LSR300 central air conditioning Computer Control System block diagram , the system bus architecture using RS-485 mode , the computer-controlled management platform , RS-232/RS-485 converter module , control terminal 14 (including communication Board and main control system, the number of its control terminal can be increased or decreased according to actual requirements ) component . Computer-controlled management platform which is mainly used for data communications , system testing, configuration and control functions , and inquiry management. System RS-232/RS-485 converter module from the MAX-IM produced MAX491E, MAX232A composition, the module 's circuit connection shown in Figure 3 . Communication board by the MB89P475 the core composition, the structure shown in Figure 4 . Figure in RS-485 interface to the MAX491E completed, the receiver is often through the state (RE ground), strobe transmitter (DE side ) from MB89P475 the P2.7 port control ( high strobe ) . Communication board was completed for the following functions: (1 ) DIP switch used to achieve the control terminal of the address coding; (2 ) Unit of the local operation control and display (including the local inquiry , set up and control ); (3 ) , respectively communicate with the computer and the main control system , main control system to achieve data transfer between computers . Which , with the computer using RS-485 bus between the ways connect with the main control systems are connected by current loop ; (4 ) set the memory unit of information , failure information and the total running time . In addition , the system also can be used in the main control system LSR300 central air-conditioning control system for stand-alone group 4 MB89P475 Communication Software Design 4.1 Communication board and computer communication (1 ) communication protocol Communication board and computer communications using RS-485 bus connected , the communication process by a master computer , communications data using RS-232 standard data format [ 2]. When the communication board receives the correct synchronization code and address code, said that the communication board can communicate with the computer . At this point choose MB89P475 of UART/SIO2 for the UART ( two- line asynchronous ) communication mode, communication data format is defined as a start bit , 8-bit data length and 1 stop bit , no parity bit . (2 ) Software Design UART/SIO2 relevant registers initialized as follows : MOV SCR2, # 104; set the baud rate = 1200bps ( system clock Fch = 8.000MHz) MOV SMC21, # 00001011B; select UART mode , 1Bit stop bit , 8Bits data length , no parity bit MOV SMC22, # 01111010B; allowed to receive interrupts , interrupt prohibiting launch , launch permits, to receive permit Launch inquiry conducted by the data that put the main program loop subroutine launch , launch through the query data register empty flag bit TDRE to decide whether the data written to the next launch . Emission subroutine flow chart shown in Figure 5 . Data reception , interrupt manner. Interrupt service routine entry into the receiving process should be the first to receive the data according to the state of full flag RDRF interrupt request to determine whether it is due to receive error generated ( generate an interrupt when the receive data full flag bit RDRF = 0), then it was decided by the judge Is receiving data or for error handling . Interrupt service routine of the flow chart shown in Figure 6 . 4.2 Communication board and main control system communication (1 ) communication protocol Communication board and main control system of communication be achieved with current loop , this can enhance the reliability of communication. Master by the communication board communication process , communication of data using RS-232 standard data format [ 2]. Choose MB89P475 of UART/SIO1 for the UART ( asynchronous two- wire ) communication mode, communication data format is defined as a start bit , 8-bit data length and 1 stop bit , no parity bit . (2 ) Software Design Related registers initialized as follows : MOV SCR1, # 52; set the baud rate = 2400bps ( system clock Fch = 8.000MHz) MOV SMC11, # 00001011B; select UART mode , 1Bit stop bit , 8Bits data length , no parity bit MOV SMC12, # 01111010B; allowed to receive interrupts , interrupt prohibiting launch , launch permits, to receive permit Specific programming and communication boards and computer programming in the same way of communication . 5 Conclusion Although MB89P475 Dual UART / SIO structure is flexible , safe features, but a reasonable program design is also crucial. Set in LSR300 central air-conditioning control system computer to MB89P475 core design communications boards , full and rational use of the MB89P475 Dual UART / SIO resources . It can be used as the control terminal and computer data exchange hub , but also to avoid duplication of main control system development . Currently the system has been put into use, its convenient and flexible operation mode and the safe and reliable operation has been affirmed by users .