51 series is currently the most widely used 8-bit microcontroller family , its rich development resources and lower development costs , so that 51 computers are now and in the future will still have strong vitality. Rapid development in network technology today, the real work will be 51 computers in the system needs access to the network . As the 51 Series Microcontroller is not integrated Ethernet interface , therefore, how to access network 51 computers systems is a topic worth exploring , the key is how the MCU hardware interface with the Ethernet controller . This article will discuss the topic .
Ethernet Controller Ethernet controller is a consistent standard IEEE802.3 Ethernet controller , with RTL8019, RTL8029 and RTL8139 series . RTL8019 ISA bus which is more easily achieved with the 8-bit MCU interfaces . RTL8029 and RTL8139 is a PCI bus , not directly with 8 -bit MCU interface adapter requires a PCI interface . Given the current RTL8029 easier to buy in the market , so it RTL8029 ethernet controller as the network interfaces . RTL8029 already contains the entire internal network interface layer protocol (PHY layer and MAC layer protocol ), so apply it simple .
Users do not consider the link control problem, just consider how the microcontroller to read from the RTL8029 in the TCP / IP protocol of the data can be . Standard PCI bus signals are 3.3V and 5V standard , a number of signal lines , but not all PCI devices use all of the PCI interface signals , in fact, you can only use them in need . RTL8029AS Ethernet controller to follow standard 5V and only use the PCI bus signals in the following sections :
AD [31:0] - data signals multiplexed bus .
FRAME - frame period signal , by the current master device driver , said the start time and duration of visit .
IRDY - master ready signal .
TRDY - ready signal from the device .
C/BE-- bus command and byte enables multiplexed signal . Address of a bus command , byte enable data period .
IDSEL - initialize the device select signal . During the read and write transfers in the parameter configuration for chip select . Only one PCI device for the situation , it can always take high .
RST - reset signal .
CLK - system clock signal , the frequency range of DC ~ 33MHz. Above the rising edge of CLK signal are valid .
INTA - interrupt request signal , RTL8029 data ready can be used to send interrupts to the host controller .
DEVSEL - equipment selection signal that drives the equipment it has become the current access device , as in the SCM system , RTL8029 is a single PCI device , so the signal can not .
PCI interface design
Ethernet controller interface signals , in addition to address the external data bus is bidirectional , TRDY signal generated by the Ethernet controller , the direction from the Ethernet controller to the PCI interface; the remaining part of the signal generated by the interfaces , Direction is from the PCI Interface to Ethernet Controller . Interface design thinking is: can the PCI interface to external memory as a single chip approach , microcontroller to read and write external memory read and write timing of the PCI interface , PCI interface by the timing of this read and write operations into a PCI timing right to Ethernet controller to operate. MCU operation during external memory signals used PO mouth , P2 I , ALE and RD and WR signals . Where , P0 port for the address (low 8 bits ) / data multiplexing , P2 port for high 8-bit address signal ; ALE for the address latch signal is high when the value of P0 port latch to the lower 8 bits of data online ; RD and WR signals for the read and write effectively , active low . Therefore , PCI interface, in fact play an 8-bit microcontroller to read and write from a 32-bit PCI read and write timing to the role of sequence conversion , block diagram shown in Figure 1 , to visit project timing shown in Figure 2 .
In Figure 2 , you can complete the configuration of PCI devices to access and I / O read and write access, as long as both can access the MCU operation on RTL8029 . IDSEL signal is only in the configuration before starting the interview for months, in the I / O access is not used in the signal. FRAME effective after the first clock edge is the address of the beginning . At this point in the AD bus transfer address , the C / BE bus transmitted commands . IRDY immediately after the data valid period of time in the AD bus on the transmission of data , in the C / BE bus transfer byte enabled. But the data transmission is also effective in the IRDY and TRDY the clock forward to . Byte enables 32-bit data specified time line in which a data byte of data is valid . Reading of the configuration process: first to send address, send the command ( the command value of 1010B) and byte enables, read the contents of the configuration space . Write configuration process: first to send addresses , send the command (command value 101lB) and byte enables, sending configuration data . Read I / O process: First, send address, send the command ( the command value of 0010B) and byte enables, read I / O space in the content . Write I / O process: First, send address, send the command (command value 001lB) and byte enables, sending data . In I / O interview , AD [1: O] both have special requirements , needs and C / BE [3:0] match . When the C / BEO valid , AD [1: O] must be 00 , when C/BE3 valid , AD [1:0] must be 11 . In the specific visit, whenever a device address decoding is selected , they should check whether the byte enable signal AD [1:0] line . If the two conflict , the entire visit will not be completed. Therefore, the write PCI bus, microcomputer software necessary to refer to this part of the agreement on the content , the Ethernet controller to operate correctly . Bus Command / Byte Enable (C / BE) registers the address valid after one cycle , FRAME signal , effectively , that address the beginning , C / BE [3:0] bus for the bus command , address period can Lasted only one period , and then immediately enter the data period . In SCM systems can not be considered to support the complex PCI data bursts , into the data period , FRAME signal immediately back to high , then C / BE [3:0] bus to byte enables . FRAME signal can therefore bus command / byte enable register address signal to generate . IRDY signal in the data period to be effective , it also can be IRDY bus command / byte enable register address signal to generate or generated by the FRAME signal . IDSEL signal only with the configuration access , and therefore can command bus command word to generate . In the I / O access time . Word of the highest order bit3 is O; in the configuration interview . Word of the highest order bit3 to l. Therefore, we can use this bit to generate IDSEL signal . Also have stated earlier , can be used as external memory PCI interface, to access , therefore , from the 8-bit data into 32 bits of data. PCI interface to design the following registers : Register 0, corresponding to 32-bit data / address bus AD [7:0], for writing ; Register 1, corresponding to 32-bit address / data bus AD [15:8], to write ; Register 2 , corresponding to 32-bit data / address bus AD [23:16], to write ; Register 3 , corresponding to 32-bit data / address bus AD [31:24], to write : Register 4 , corresponding to 32-bit data / address bus AD [7: O], for the time ; Register 5, corresponding to 32-bit data / address bus . AD [1 5:8], for the time ; Register 6, corresponding to a 32-bit data / address bus AD [23:16], for the time ; Register 7 , corresponding to 32-bit data / address bus AD [31:24], for the time ; Bus Command / Byte enable register , corresponding to C / BE [3:0]; Reset registers , used RTL8029AS hardware reset operation . Based on the above analysis, must PCI interface, block diagram , shown in Figure 3 .
3 interface VHDL implementation PCI interface VHDL code, you can contact us.Under the above code Qaartus II compiled and consolidated , taking up 149 macrocell resources , can be used to complete the CPLD device MAx7l60 .
4 Conclusion Design method described in this paper has been successfully used in radio remote control monitoring system , access to Ethernet MCU system through 5l , realized in the network no one on the remote control room equipment .