Abstract : TLC5510 is Texas Instruments (TI) produced eight half- flash ADC structure , which uses CMOS process, can provide minimum 20Msps sampling rate . It can be widely used for digital TV, medical imaging , video conferencing , high speed data conversion, and QAM demodulator and so on. This paper introduces the TLC5510 performance indicators , pin functions , internal structure and operation of timing , given the application TLC5510 reference voltage circuit design and configuration . Key words : high-speed AD conversion; data acquisition ; TLC5510 1 Overview TLC5510 TI produced by the American pieces of the new ADC (ADC), which is manufactured using CMOS technology high-impedance parallel 8-bit A / D chip minimum sampling rate of 20MSPS. As the TLC5510 Flash using semi- structure and CMOS process , thus greatly reducing the number of comparator devices , and high-speed conversion while maintaining low power consumption. In the recommended operating conditions , TLC5510 consumes only 130mW. As the TLC5510 is not only high-speed A / D conversion , but also with internal sample and hold circuit , which greatly simplifies the design of the external circuit ; the same time , because of its internal resistor divider with a standard , so the power from the +5 V Be 2V full scale reference voltage . TLC5510 can be applied to digital TV, medical imaging , video conferencing , high speed data conversion, and QAM demodulator and so on . 2 internal structure and working principle of pin- description Pin description 2.1 TLC5510 TLC5510 24- pin , PSOP surface-mount package (NS). The pin arrangement shown in Figure 1 . The pin functions are as follows : AGND: Analog ground ; ANALOG IN: analog signal input ; CLK: clock input ; DGND: Digital signal ground ; D1 ~ D8: data output port . Lowest for the data D1 , D8 for the highest ; OE: output enable terminal . When OE is low , D1 ~ D8 data effectively, when OE is high , D1 ~ D8 as the high impedance ; VDDA: Analog circuit power supply ; VDDD: Digital circuit power supply ; REFTS: one of the internal reference voltage terminal , when using the internal voltage divider rated 2V reference voltage generated when the short circuit to REFT this end ; REFT: The second reference voltage terminal ; REFB: The third reference voltage terminal ; REFBS: internal reference voltage terminal of the fourth , when using the internal voltage reference generates the nominal reference voltage of 2V , this side short circuit to REFB side . Figure 2 Figure 3 Click to enlarge 2.2 TLC5510 internal structure and working process TLC5510 internal structure shown in Figure 2 . Can be seen from the chart : TLC5510 ADC includes clock generator internal voltage divider , a set of relatively high 4-bit sampling , encoder , latches , 2 sets of samples with low 4-bit comparator, Encoder and a low 4-bit latch and other circuits . TLC5510 external clock signal CLK through its internal clock generator can produce 3-way internal clock , to drive the comparator group 3 samples . Reference voltage divider can be used for these three groups to provide reference voltage comparators . Output A / D signals from the high- high four 4-bit encoder directly , while the lower 4 bits of sampled data from two low- 4 encoder to provide alternate . TLC5510 timing of work shown in Figure 3 . Clock signal CLK falling edge capture every analog input signal . The first N times the data collected through the 2.5 clock cycle delay, will be sent to the internal data bus . Work shown in Figure 3 under the control of timing , when the first arrival of the falling edge of one clock cycle , the analog input voltage will be sampled to the high block and low comparator comparator block , the high comparator block in the second clock cycle The rising edge of the final data to determine high , while the low reference voltage generation and high voltage corresponding data . Comparing the low block in the third clock cycle, the finalization of the rising edge of low data . High data and low data in the fourth rising edge of clock cycles are combined , so that the first N times the data collected through the 2.5 clock cycle delay, can be sent to the internal data bus. At this point , if the output enable OE effective , the data can be sent to the 8-bit data bus. Since the maximum CLK cycle 50ns, therefore , TLC5510 DAC minimum sampling rate can be achieved 20MSPS. 3 -line array CCD data system Figure 4 a typical external circuit for the TLC5510 . Figure of FB1 ~ FB3 as high-frequency magnetic beads , analog power supply AVDD through FB1 ~ FB3 for the three parts of the analog circuit to provide operating current to get better high-frequency decoupling effect . The author developed the linear array CCD data acquisition system consists of timing generator , CCD drive circuit , video signal pre-processing circuit and the ADC, data storage , PC machine, etc. TLC5510 high-speed , internal sample and hold circuit with the characteristics to make it more conducive to the design . TLC5510 's primary role is to high-speed CCD output analog video signal into its analog amplitude of the corresponding 8-bit digital video signal . Figure 5 is the author of the design of video signal A / D converter TLC5510 peripheral circuits . TLC5510 can use two kinds of external and internal reference voltage connection method. In which the external reference voltage from pin REFT and REFB access , and should meet : VREFB +2 V = VREF = VDDA 0 = VREFB = VREFB-2V 2V = VREFT-VREFB = 5V Start from zero level for the positive polarity analog input voltage , REFB should be connected to the analog ground AGND. VREFT range from 2V ~ 5V. To simplify the circuit , can use the inner part of the TLC5510 resistor from the analog supply voltage VDDA made reference voltage . In this design , CCD output analog video signal through the inverting , filtering, amplification shall be from the zero level after the start of the positive polarity analog voltage signal . Therefore , in order to simplify the circuit and meet the design requirements , I chose the TLC5510 internal reference mode , the same time, because the CCD video signal is a 2V reference so, according to TLC5510 's own characteristics, in the design process , the author REFBS side and AGND , but will REFTS connected with VDDA side , while REFBS shorted to REFB side , REFTS shorted to REFT side to get the 2V reference voltage . In using the data acquisition system to collect data in the process, when the CCD output video signal output , generated by the timing generator, A / D conversion control clock CLK synchronous control , TLC5510 will differential amplification, low-pass filter CCD analog video signal after conversion to its real-time simulation of the amplitude of the corresponding 8-bit digital signal , when the TLC5510 output enable OE is low and the high-speed data memory write control and address decoding control are effective , the system The results can be converted into high-speed data storage in order to wait for the PC machine to read . In order to CCD output video signal can be accurate and reliable conversion and storage , in the design process , the author of the TLC5510 's job control clock CLK, the output enable OE and high-speed data memory address decoder control clock, the clock cycle to read and write control Made a specific time budget , and the logic of the phase relationship between them has done a detailed study . According to the budget , I would counter within the timing generator , comparator, logic gates and D flip-flop , etc. and logical combination of frequency and level , and thus to produce accurate and reliable temporal logic . System and data analysis results show , with TLC5510 as a linear CCD video signal A / D converter chip , the interface circuit is simple and practical , easy to use , good stability . Figure 5, video signal A / D converter external circuit Click to enlarge 4 Conclusion In the TLC5510 ADC and the line array CCD Data Acquisition System Design , the author summed up as follows by experimental experience : (1 ) In order to reduce system noise , external analog and digital circuits should be separated and should be shielded as much as possible . (2 ) because the chip TLC5510 AGND and DGND are not connected internally , so these pins need to be connected externally . In order to pick up the smallest noise , the best to separate the twisted-pair cable for the power cord. Meanwhile, in the printed circuit board layout should also use the analog and digital ground plane . (3) VDDA to between AGND and DGND VDDD to be respectively 1µF decoupling capacitor , ceramic capacitor is recommended . For analog and digital ground , in order to ensure solid noise -free ground connection , tests should be careful . (4) VDDA, AGND and the ANALOG IN pin should be with the high-frequency pin CLK and D0 ~ D7 isolated . In the printed circuit board , AGND traces on the ANALOG IN should be as much as possible on both sides of the alignment for shielding purposes. (5 ) To ensure the TLC5510 's work performance, system power is best not to use switching power supply.