Abstract : AD9430 is AD Introduces 12-bit ADC , which uses a single 3.3V power supply CMOS and LVDS offers two interface modes . This paper introduces the main properties of AD9430 , given its two LVDS and CMOS output modes of the application circuit . Keywords : AD converter ; dual data port output ; LVDS AD9430 1 Overview AD9430 is AD launched a 12-bit high-speed , low power A / D converter. It uses a single 3.3V power supply , thus simplifying the system power supply design . AD9430 on-chip reference voltage source and comes with sample and hold device to the system design easier to use. The device provides two data output interface mode , the dual-port 3.3V CMOS output and LVDS output . In the CMOS mode, each channel 's data rate by 105 MSPS, and have alternate data output and the parallel data output in two ways ; in LVDS mode, data through the rate of 210 MSPS, with FP with the LVDS receiver -GA -chip directly interfaces . A binary encoding format output data complement and offset binary code formats to choose from. One of the LVDS interface ( ie low-voltage differential signaling Low Voltage Differential Signaling) is a low -swing current-mode differential signal , which allows the signal lines on the PCB in the differential or balanced cables to transmit hundreds of Mbps, while the low pressure Rate and low current drive output can achieve low noise and low power consumption . AD9430 main features are as follows : ? Using 3.3V single power supply ; ? analog input frequency of 65MHz, the sampling rate of 210MSPS , the SNR up to 65dB; ? sampling rate of 210MSPS , the power consumption is only 1.3W; ? to provide data synchronization clock input and data output ; ? built- clock duty cycle stabilizer ; ? has excellent linearity : DNL = ± 0.3LSB INL = ± 0.5LSB shows the internal structure and pin Figure 1 , Figure 2 were used for the AD9430 CMOS mode and LVDS model of pin distribution . The main pin as follows: S5: full scale adjust pin , then high , the input differential signal peak value 0.768VP-P; then low, the input differential signal peak value 1.536VP-P. S4: to use the CMOS mode , then high for the alternate data output , low access to parallel data output ; the feet grounded in LVDS mode . S2: Output mode selection , low access to dual-port CMOS output mode; then high for the LVDS output mode . S1: output data format selection , then low to offset binary code; then high for the binary complement . Figure 3 LVDS mode timing diagram Click to enlarge SENSE: Reference Voltage mode select pin , use an external reference voltage, to take high ; suspension is used when the internal voltage reference . VREF: Reference voltage input pin , the decision by the SENSE pin can provide a stable internal 1.23V reference voltage , low noise ; When using an external reference voltage should be ground using a 0.1µF capacitor connected to the external reference voltage , the capacitor Capacity of deviation should be within ± 5% . Note: The full-scale adjustment range and the reference voltage is linear proportional relationship . VIN +, VIN-: differential analog signal input . DS +, DS-: In the CMOS mode, the pin can be used for differential data synchronization (input ) . When the DS + pick high , DS- connected low, , A / D converter data output and clock remain the same . When the DS + and tHDS tSDS the clock falling edge between , the synchronization started , and in LVDS mode, should be DS + ground , and DS- accept 3.3V. CLK +, CLK-: clock input pin . When the clock frequency is less than the nominal value of 30MHz , the chip comes with a clock duty cycle stabilizer will not work ; when the input clock frequency of dynamic change, the need to wait for 1.5µs ~ 5µs, can be valid data (this Is immutable) . The differential input clock can also be single -ended input , in order to get better dynamic performance , the best differential input . LVDSBIAS: LVDS current output . In LVDS mode, the end of the ground should be added a 3.7kO resistor . DA0 ~ DA11: CMOS mode, the A -side data output . DB0 ~ DB11: CMOS mode, the B -side data output . OR-A, OR-B: namely A, B ports overrun flag . D0-, D0 +, ... ... D11-, D11 +: LVDS mode, data output . DCO +, DCO-: data output clock . In the CMOS mode, the clock frequency output signal 2 , by the DCO + and DCO- two-port output, the clock output signal can easily latch and latch the input clock distortion is very low, but the on-chip clock buffers can drive large 5pF capacitor in ; in LVDS mode , the output clock with a clock frequency of the input differential signal , application should be terminated at the receiving end of a differential 100O resistance . Figure 5 CMOS mode timing diagram Click to enlarge OR-, OR +: LVDS mode, the overrun flag . AGND: Analog ground . AVDD: Analog power supply . DRVDD: 3.3V data power , the range of 3.0V ~ 3.6V. DRGND: data to . DNC: empty legs . 3, timing and application of circuit operation 3.1 LVDS mode, the interface circuit Figure 3 for the LVDS mode timing diagram. In LVDS mode, the output clock with a clock frequency of the input differential signal; the relative input clock signal has a delay of up to 5ns ; the first N points of the analog signal sample after 14 cycles after the data output ports . Figure 4 shows the AD9430 in LVDS mode, the typical connection . To get the best dynamic performance , should enable VIN + and VIN- in impedance matching . Differential analog input required to drive ; if the input is single-ended signal , it will greatly reduce the signal to noise ratio and signal - noise distortion ratio . To this end, broadband transformers can be used (such as Minicircuit company ADT1-1WT) to single-ended signal is converted to differential signal . The nominal peak value of the input circuit : single-ended signal to 1.5VDIFFP-P, differential signal 768mVp-p × 2. Should be terminated using a 3.7O in LVDSBIAS grounding resistance , the resistance of the current in the chip through the amplification for each output port providing a 3.5mA output current- mode driver to drive then there is 100O differential termination circuit And, ultimately, for the receiver provides a voltage of about 350mV . Figure 6 CMOS output mode Typical connection diagram Click to enlarge 3.2 CMOS mode, the interface circuit Figure 5 in CMOS mode timing diagram. The figure shows that when the falling edge of sync pulses DS + appears in the range and before the next clock rising edge , its sampling of analog signal N will appear in 14 clock cycles after the output from the alternate mode of the port A output; then Down a sampling point N +1 at 14 cycles from the port B output . In the parallel data output mode, the first N sampling points of data after 15 cycles of the output from the A port and the output time with the first N +1 sampling points of data from the 14 cycle time from the B port output The same . Figure 6 for the AD9430 in the CMOS mode, turn out the way a typical connection diagram . Data synchronization input signal power on reset signal can be achieved ; as AD9430 output data transfer speed is very fast and should therefore be latched at the output port plus a circuit to ensure the accuracy of the data received .