Abstract: Details the Purple Mountain Observatory infrared CCD camera system developed in the laboratory hardware and software design. According to Kodak chip KAF-0401LE CCD timing requirements, with a complex programmable logic device (CPLD) to achieve the CCD timing; reduced by correlated double sampling noise detection signal; with 89C51 for the lower machine control, communication with the host computer via RS232; system control software written using Visual C + +.
Key words: CCD CPLD correlated double sampling serial communication control system
Introduction
CCD is usually divided into three grades; commercial-grade, engineering grade and science class. 3 levels than a high-level requirements. The performance of CCD to measure the following aspects: quantum efficiency and responsiveness and detection of degree of noise equivalent power, the dynamic range and charge transfer efficiency. Scientific grade CCD with its high photon conversion efficiency, broadband spectral response, good linearity and wide dynamic range is widely used in astronomical observations, the telescope has become an essential back-end test equipment. Observatory telescope domestic terminals are complete sets of equipment from external causes, use and maintenance is very convenient, and expensive, therefore an urgent need to develop their own domestic CCD technology. Purple Mountain Observatory infrared laboratory of this topic in-depth research, extensive research, careful selection,
from the chip to the system hardware and software has been designed to build their own CDD camera system.
1 System Design
CCD chip camera system performance decision, for our extensive research, the final selection of Kodak KAF-0401LE chip. Its large dynamic range (70dB), charge transfer efficiency (0.999 99), wavelength range is wide (0.4µm ~ 1.0µm), low dark current (at 25 ? under, 7pA/cm2), quantum efficiency of 35% and has anti-saturation, to meet the requirements of scientific observation, both for spectral analysis, but also for imaging observations.
System design focused on addressing the CCD chip of the drive and system noise problems. Our designs are as follows: The Kodak KAF-0401LE chip as a detector, Ateml company with Flash Flash for the next crew of the 89C51 controller for complex programmable logic (CPLD) for the timing and address decoding occurs, the use of correlated double sampling techniques to reduce noise, built to keep the 12-bit sampling A / D converter AD1674 analog to digital conversion along, extended 8 128Kbit (628128) of RAM as a temporary space for the frame, with the computer through RS232 serial communication, accept the computer control. The system consists of several functional components shown in Figure 1 form.
Timing Signal Generator 1.1
KAF-0401LE chip timing requirements: integration during the fV1, fV2 remain low; lines remain high during the transfer fH1, fH2 remain low. Start each line the first two pulses fV1 after the falling edge, there must be a line transfer setup time tfHs, after reading the line to be delayed one pixel time te begin the next line fV1 pulse; Similarly, fV1 2 min pulse falling edge , we began to transfer the next line, so until you finish one.
Complex programmable logic device (CPLD) for its highly integrated, flexible, convenient features, and in the circuit design more and more widely used. Altera's programmable logic device EPM712SLC84-15 is available with 2500 gates, 128 macrocells, 8 logic blocks, the maximum clock of up to 147.1MHz, with 68 available for users of the I / O pins PLCC packages can be programmed through the JTAG interface online. We use EMP7128SLC84-15, through hardware description language (VHDL) in the integrated development environment MAX PLUS II to complete the logic design; compiled, downloaded through the JTAG interface, to the circuit board EPM7128SLC84-15, the realization of the KAF-0401LE chip timing requirements.
MAX PLUS II Although there is a rich component library, but not for a particular application developed with versatility, it is inherent in the library call may result in waste of resources, not necessary. So we follow the requirements, the preparation of his own library, and then call in the program as a component. In this system, only 1 EPM7128LC84-15 to achieve the CCD timing requirements, and interfaces extend the temporary RAM chip 8255 and chip select address decoding, not only simplifies the hardware design of the circuit shame, improve system reliability, and reducing costs. The requirements for AC timing conditions listed in Table 1.
Table 1
Description Symbol Minimum Maximum normal
fH1, fH2 clock frequency / MHzfH 1015
fV1, fV2 clock frequency / kHzfV 100125
Cycle / nste67100
fH1, fH2 setup time / µstfHS0.51
fV1, fV2 pulse / µstfv45
Reset Clock Pulse Width / nstfR1020
Read time / mstreadout3450
Read each line time / µstline65.895.6
1.2 Double Take, analog amplifier and A / D converter
We used to meet the requirements of high-frequency amplifier LF356N design double sampling and analog amplifier circuit. Selected according to the dynamic range of CCD own 12-bit sample and hold A / D converter for analog-digital conversion AD1674.
Figure 2 shows the principle of double sampling. RSL is the CCD reset level, the light signal is equivalent to the difference between SGL and the RSL, in theory, as long as the RSL and SGL, respectively at each sampling time, and then subtracting the value they get the signal. However, in fact, is not ideal SGL RSL and horizontal, but the existence of low-frequency fluctuation noise. To reduce noise, the usual practice is, respectively, and the SGL at the RSL averaging multiple samples, so that the data processing hardware and software requirements are very high. We used here the integral correlated double sampling techniques, as shown in Figure 3, CCD signal through the same phase and are connected to the analog switch inverting amplifier input. Analog switch S1 is open, RSL through a capacitor integral; s2 open, SGL signal integration by the capacitor; s3 open the input is grounded, the signal remains unchanged; s4 for the reset switch. Integral amplifier input and output relationship is as follows:
Figure 2 points in the correlated double sampling output is the output waveform. After the sample and hold through the A / D analog to digital conversion, by 8255 there board RAM.
1.3 voltage bias circuit
CCD drive signal DC bias voltage varies, CPLD TTL signal generated by the voltage change must be added to the input of the CCD. We first use the LM317 and LM337 produce the desired bias voltage, and then after the converted clock driver chip DS0026 timing and bias are in line with the requirements of CCD signal, the circuit shown in Figure 4.
LM317 for output offset voltage positive phase, LM337 for the negative phase output offset voltage, the resistance by adjusting the variable resistor R2 we get the required bias voltage is calculated as follows:
Which, Iadj <100µA, Vref = 1.25V, Figure 4 (a) in the R1 take 240O, Figure 4 (b) in the R1 take 120O.
2 software programming
Is to manage the hardware, software, tools, hardware is the foundation to achieve software function. The heavier the system software tasks, from programmable logic device programming hardware description language, the exchange board microcontroller programming language programming to the computer control system for Visual C + + programming.
2.1 programming language VHDL timing signal
We are prepared to use CCD clock drive signal VHDL, image buffer RAM and interface expansion chip address decoder 8255 and the chip select signal, the integrated development environment to compile MAXPLUS II, through the JTAG port to download to EPM7128SLC84-15 in the. Here are some of achieving CCD system timing VHDL language design and timing simulation results. VHDL language programming is basically divided into two parts: the physical description and structure definitions. Entity that part of the definition of the port, the structure to implement the logical design. Procedures are as follows:
LIBRARY ieee; - including the library
USE ieee.std_logic_1164.all;
USE ieee.std_LOGIC_ARITH.ALL;
USE ieee.std_logic_unsigned.all;
ENTITY kodak7128 IS - part of an entity that
PORT - Port
(Clk: IN std_logic; clock input
start: IN STD_LOGIC; - Start collecting data entry
rc: OUT STD_LOGIC; - Start A / D conversion output
s1, s2, s3, s4: OUT STD_LOGIC; - correlated double sampling mode clock output
v1: OUT STD_LOGIC; - CCD line transfer clock output
v2: OUT STD_LOGIC;
r: OUT STD_LOGIC; - CCD output is always reset
h1: OUT STD_LOGIC; - CCD pixel output clock signal conversion
h2: OUT STD_LOGIC;
a, b, c: IN STD_LOGIC; - Extended RAM decoder input
a2, a3, a4, a5, a6, a7: IN STD_LOGIC; - Expansion of the chip address decoder chip select input 8255
a8, a9, a10, a11, a12, a13, a14, a15: IN STD_LOGIC;
ram5, ram6, ram7: OUT STD_LOGIC; - Extended RAM and 8255 election decoding output
ram8, ram9, ram10, ram11, ram12, cs8255: out std_logic);
ARCHITECTURE mboard OF kodak7128try IS-structure to achieve some
- PROCESS custom logic
END mboard;
Timing simulation results shown in Figure 5.
2.2 The next crew of the assembly language programming
89C51 as the soul of the board, came to receive computer commands, management of CCD data collection, reception, transmission. Communication with the computer through the serial port interrupts, data collection via external interrupt implementation.
Need a computer with pre-defined communication protocol with a single dispatch, in the initial program set the baud rate communication stack is initialized and registers the initial value, and then into the loop, waiting for the occurrence of an interrupt, the interrupt subroutine is called to achieve scheduled function.
When the computer has a command arrives, enter the serial interrupt routine, interrupt, in accordance with pre-determined in good agreement, sent the computer to determine the different commands, different subroutine calls. One of the commands are: collection, stop acquisition, taking the number of stops to take a few.
2.3 CCD Camera Control System for Visual C + + programming
Windows with its simple and friendly graphical interface became the most popular operating system. Visual C + + is now recognized as the most powerful Windows programming tool. We use it to develop a camera control system.
First, the definition of man-machine interface interface. In the program is divided into data acquisition, storage and processing areas, the data acquisition aspects of our specific definition of a serial communications, serial port to open a thread for monitoring events, for the down-bit microcontroller to send commands and receive data.
3 test results
We completed the system from the chip to the camera hardware and software development, preliminary testing, the effect is good, for the development of CCD technology to make our own sense of exploration and research. Figure 6 is a CCD camera quantum efficiency test results.
