Abstract:
This paper presents a DSP-based ADmC812 and data acquisition system design. System uses the master-slave design, DSP and ADmC812 common between the SRAM through the exchange of data can meet the data collection capacity, computational complexity, real-time demanding applications.
Introduction
ADmC812 is ADI's to 8051 (8052) for the control of the core kernel of new micro-converter. As ADmC812 integrated a large number of internal peripherals. It is itself a fully programmable, self-calibration, high accuracy data acquisition system that can replace the traditional MCU + A / D + ROM + RAM high-cost, large volume products, especially its high precision and high speed A / D module, especially adapted to intelligent sensing, instantaneous access, data acquisition and various communications systems. However, sampling a large volume of data, computational complexity, they require a higher real-time occasions, as in the structure and speed constraints, are often unable to meet the requirements. In this paper this situation, the DSP-based ADmC812 and data acquisition system. In this system, ADmC812 as a host to complete the ADC, DAC, display, keyboard functions, DSP as slave, focusing on complex data operations, both through common SRAM for data exchange and communications.
Figure 1 System structure diagram
ADmC812 and TMS320F206 Introduction
ADmC812 micro-conversion chip
ADmC812 is a 16-bit counter / timer and 32 programmable I / O interfaces 8051/8052 micro-controllers, including an 8-channel, 5ms conversion time, precision self-tuning, 12-bit successive approximation ADC; 2 12-bit DAC, 10.5KB flash EEPROM, 256 bytes of SRAM. Also includes a number of important modules, such as watchdog timer and power monitor, ADC and DMA mode between the data memory, storage, protection, a universal asynchronous serial transceiver (UART), SPI and I2C bus interface.
ADmC812 in rich peripherals, it does not require external bus can be extended to form a complete data acquisition system, a high cost. More noteworthy is that in ADmC812 integrates 12-bit high-precision 8-way, self-calibration 4ppm / ℃ the ADC circuit. And, when working conditions (such as clock frequency, analog input reference voltage or power Dianya) changes, tsing the software right ADmC812 correction within four special function of the register settings, ADC to achieve the purpose of further correction. ADmC812 by setting ADCON1 ~ 3 3 special function registers, ADC can operate in 3 different modes, to achieve single conversion, continuous conversion mode, and DMA A / D converter, you can choose according to specific needs, in DMA mode , allowing each to set ADC register ADCCON1 ~ 3 consecutive samples and the results are written to external RAM. This auto-capture feature to greatly facilitate the master-slave data exchange between processors.
Digital signal processor TMS320F206
TMS320F206 (hereinafter referred to as F206) is a TI TMS320C2000 series DSP produced one. After following the C2X and C5X launch low-cost high-performance 16-bit fixed-point DSP, because it uses a modified Harvard architecture with separate program bus and data bus, with four pipeline operations, its operating speed of up to 40MIPS, with Characteristics of high-speed operation. While providing a rich instruction set, enhanced modular design, making it universal is increased, the applications continue to expand, which has become an ideal substitute for high-end single chip. F206-chip with 32K of Flash memory, comes with users F206 in line with IEEE standard 1149.1 JTAG interface, you can simulate and debug the program, and to burn the code chip, greatly facilitate the user's system design and program debugging.
TMS320F206 direct memory access (DMA) functions, by using the HOLD operation allows an external program, data, and I / O space and direct memory access. The process is initiated by the two signal control. External device can drive the pin low, thus the request to the external bus control. If the break is allowed, it will trigger the interrupt. F206 in the corresponding interrupt, the software logic can be issued a response to the signal processor, said it would give up control of the external bus. According to the external address signal (A15 ~ A0), data signals (D15 ~ D0) and the memory control signal will be set to high impedance state, to achieve DMA function.
System hardware design
The hardware structure shown in Figure 1, as the DSP global memory 62 256 data memory, but it is also ADmC812 external memory through the bus and the two controllers are connected to data memory 62256 and realize shared memory. In order to ensure that the two controllers can work independently. And 62,256 in ADmC812 inserted between the four 74HC245 for bus isolation. Thus, under the control of the ADmC812, each time only one controller to access 62256. The figure 62,256 as ADmC812 external memory, A15 for the chip select signal, the address range is 8000H ~ FFFFH; as the F206's global data memory chip select lines for the use of the high-end 32K word address range (8000H ~ FFFFH). 2 Select the signal through a gate and 62 256 non-selected line CS2 chip connected to chip select signals to achieve separation.
ADmC812 through P1.0, P3.2 (INT0), respectively, and DSP's, XF pin is connected to the DSP application by the P1.0 bus control, ADmC812 in response to a request DSP, DSP's CPU is suspended, and the external bus transfer . ADmC812 open the bus driver through A15, and the door with the non-selected 62 256, control of access to 62 256, to achieve reading and writing on the 62256. The F206 can also request to ADmC812 interruption, ADmC812 in response to interrupt INT0, the associated transactions. On the other hand, ADmC812 by reading the pin level, you can confirm that F206 is to be suspended; while on foot through the control of a branch transfer to achieve F206 program to increase flexibility of the system.
Tthe whole system is divided into modules and data processing module, ADmC812 Control Services module for data acquisition, LED display, switch the input and output, analog output and serial communication functions. F206 control data processing module, the main data processing, the completion of complex algorithms. In addition, data processing results can also directly address some important export controls, to compensate for ADmC812 I / O port of the lack of speed up the speed of the system. Two relatively independent modules exchange data through 62256.
System software design
Because the system of two functionally independent module, the corresponding software consists of two main modules, ADmC812 in the program has finished loading, I entered a program to work correctly. After system initialization, the first request by P1.0 DMA operation to the F206, and the response before, ADmC812 control access to 62 256. Then, by configuring three special function registers ADCCON1 ~ 3, can ADmC812 work in different modes. Which the DMA mode, ADC can continuously convert, and capture the value of the sample to the external RAM space without any intervention from the microprocessor, the DMA interrupt bit ADCCON2.7 that the end of conversion. In the A / D conversion and the end of the number of sampling points for the intended after, ADmC812 to break through the ADC to give up control of the 62256 and notify the DSP for data processing. Then ADmC812 into shows key functions, I / O operation, serial communications, transactional work.
F206 ADmC812 the DMA receives a request to enter the wait state, and give up control of the external bus. 62 256 sample data obtained by ADmC812, when the sampling end, DSP from the wait state to return to normal operating state and get control of the bus, data processing, to write the results back in 62 256. F206's DMA operation is: F206 pin / on to get a valid falling edge, when the CPU unit transferred to 0002H address, CPU interrupts from the 0002H address extraction unit vector and enter the interrupt service routine, in the MODE = 0 for a successful test After the interrupt service routine on the implementation of an IDLE command, make F206 into the wait state. When detected / feet after a rising edge, CPU out of IDLE state, and to external bus to return to their normal state, the implementation of data processing procedures.
Software using C language design, were conducted in two developing systems programming and debugging. Using ADI provides software development tools, can quickly and efficiently complete the ADmC812 application design, and through ADmC812 universal serial line debugging and code download. F206 with Wintech provided TDS-510 software development tools for the design. Finally, ADmC812 and F206-line debugging, to complete the software development.
Conclusion
Over design, suitable for large data collection, algorithm complexity, real-time requirements of certain applications. As the dual-CPU system, no additional add-dual port RAM, FIFO, and complex control circuits, reducing costs, simplifying the circuit, but also extends ADmC812 range of applications.