Summary: The design based on CPLD EPM7128 data combined converter. Which control the serial port data consolidation time counter circuit and the parallel data into serial data shift circuit is completed in the CPLD , the data block the merger by the appropriate software , the ultimate formation of CPM stream output . Keywords: CPLD Data Merge converter serial PCM stream High data transfer rate switch , when it and the serial port to communicate , before sending the data in two parts were sent to the serial port , and then merge the data converter through the various serial data to merge and Into a PCM stream . This article describes the design based on CPLD EPM7128 data combined converter. A data converter hardware consolidation EPM7128 is a large-scale programmable logic devices, for the ALTERA company's MAX7000 family of products , with high resistance , electrically erasable and so on , can the door unit is 2500 , the largest pin delay 5ns, operating voltage +5 V. IDT7205 FIFO Asynchronous read and write to memory chips , a capacity of 8192 × 9 bits , access time is 12ns, empty , half full , at least three flags , the maximum power consumption of 660mW, working voltage of +5 V. MSM4860DX is 5X86 PC104 embedded systems department ten days , for the AMD-133MHz CPU, with COM1, COM2 two serial ports , an LPT parallel port , a ELOPPY interface, an IDE interface, a VGA / LCD interface, an AT-KEYBOARD interface, 16 Interrupt , rated power of 8W, operating voltage +5 V. Programmable data converter circuit diagram of the merger shown in Figure 1 . The figure , DB for the data bus , AB for the address bus , R and W were to read and write signal lines , INT5, INT7, INT10 INT11 four interrupt , CS1, CS2 and CS3 is generated in the internal CPLD address decoder Addr -Encoder are sent to divider , two serial port chip select signal , ORG is a crystal oscillator pulse sent to divider , CLK is the divider output pulse FRAMECLK and PCMCLK, WFIFO, RFIFO by CPLD Contains the address information generated by FIFO read and write access to pulse , DATA_IN1 and DATA_IN2 for the serial port input data , PCM_DATA merge the data converter output PCM stream , PCMCLKA output code for the synchronous clock , WORLDCLKA synchronous clock for the output of the word . 1.3 Analysis of circuit Crystal clock pulse sent to the divider , divider contains two programmable timers . Divider to control the FRAMECLK and PCMCLK sent CPLD, the CPLD logic inside after the formation of three-way combination of pulse signal , the way control the counter form INT5, INT7 2 frame interrupt trigger pulse , CPU interrupt immediately after receiving the write FIFO; Another way to control the shift register parallel data into serial data, PCM stream ; Third Way form RFIFO to continuous time FIFO. Through two serial port interrupt (INT10, INT11) received external data, the temporary buffer zone , according to a certain format controlled by the interrupt INT5 write FIFO. 2 CPLD internal logic circuit CPLD internal logic circuit shown in Figure 2 . The figure, the dashed box the internal circuitry within the CPLD , dashed box outside the CPLD 's I / O port . 2.1 Address decoder Address decoder Addr-encoder using VHDL language generation . Addr-encoder output with the bus driver chip 74 245 the enable pulse ENB, bus transport direction enable pulse DIR, FIFO write operation pulse WFIFO, divider and the serial port chip select CS1, CS2 and CS3, FIFO data space Full marks pulse RFIFOFLAG, FIFO reset the clock pulse WCTRL. 2.2 The data shift section FRAMECLK cycle is PCMCLK 8-bit , they are sent to the pulse frequency . FRAMECLK after RP as a FIFO read signal , as the word after the two RP- synchronous clock . PCMCLK directly as a shift register 74 165 clock trigger pulse , both the output and non- low as 74,165 after heavy data trigger level . Their signal timing shown in Figure 3 . Timing diagram from the three known , whenever a byte after the last complete shift in FRAMECLK the falling edge of trigger pulse RP to read FIFO data , when 74,165 of the load is low just to be able to 74165STD ( and non- result) , the data of completion of loading, then the rising edge pulse in PCMCLK start a new one under the soft time of the data shift . 2.3 frame length counter part Design of two 74 161 long 1 / 64 divider , also known as frame length counter , the counter clock is FRAMECLK, the highest output of the counter logic and the interruption of two INT7, the AND gate output and the sub- logical differences or to interrupt high INT5. This , INT7 than INT5 before the half cycle in the timing . Start reset , INT7 pulse first generation, interrupt , COU interrupt service routine after 64 bytes of data in the write FIFO, and then shielded interrupt INT7, half cycle , FIFO in the remaining 32 bytes of data (and therefore FIFO read counter pulse and FRAMECLK the same frequency) . Then break INT5 come , CPU response, write 64 bytes of data to the FIFO, so that has been maintained in the data FIFO status ( read FIFO to avoid falls exactly between the two write FIFO , FIFO data read without a death ) . Thus, when interrupt INT5 arrival of 64 bytes are written to the FIFO, cycle , and hence as a frame length of 64 bytes . Set PCMCLK the frequency f (MHz), the FRAMECLK frequency of f / 8, as frame size is 64 , so there : frame rate = f / (8 × 64), PCM flow rate = f (bit / s). Frequency divider ratio set by software , so the rate of programmable PCM stream . 3 Software Design outp (0x303, 0x36); / / Mode 3 , square wave . / / outp (0x300, 0x50); / / timer0, frequency division ratio of 80 . / / outp (0x300, 0x00); outp (0x303, 0x74); / / method 2 , pulse . / / outp (0x301, 0x08); / / timer1, frequency division ratio of 8 . / / outp (0x301, 0x00); Data Merge: if ((com1_count% 24) = = 0); / / Serial Port 1 Frame 24 bytes of data on an array of 4 to 27 position. / / { com_buf1 [com1_count + +] = db1; / / serial port 1 receive data / / int Original_Counter; Original_Counter = com1_count/24; memcpy (Frame [Original_Counter-1] +4, & com_buf1 [com1_count-24], 24); } if ((com2_count% 24) = = 0); / / Serial Port 2 24 bytes of data in an array of Frame 28 to 51 positions. / / { com_buf2 [com2_count + +] = db2; / / serial port 2 to receive data / / int Original_Counter; Original_Counter = com2_count/24; Memcpy (Frame [Original_Counter-1] +28, & com_buf2 [com2_count-24], 24); / / Frame combined data on the array . / / Write FIFO: void Send_To_Fifo (int number); / / Send_To_Fifo function as part of the interrupt service routine . / / { for (int i = 0; i <64; i + +) outp (WFIFO, Frame [number] [i]); / / Array send FIFO, for data merge / /