Figure shows the energy-saving lighting control circuit. Integrated control circuit IC1 with quartz clock, quartz clock operating voltage because only 1.5V, the output can not meet the required stepper motor pointer drive pulse signal. Thus, VD1, VD2, C3 will be elevated to the ground IC1 2.1V, 1.5V to work in the normal state of IC1. IC1 output pulse signal from A through VT, R1, R2 inverting buffer consisting of plastic, the output from the B point of the back of digital integrated circuits to meet the second pulsuare wave signal, the A, B point of the output waveform shown below .

M-IC1 at time t1 in a high impedance state, VT cut-off; t2 moment of the M output of IC1 negative pulse, VT conduction from VT qualified collector output clock signal CLK1. A dual D flip-flop IC2, the output will be reversed back to the data input terminal D connected 2 divider, IC2-A data output terminal Q1 and IC2-B clock input CLK2 connected to form a 4 divider , the 4-frequency signal fed to IC3 for 14 min frequency, so it will be a 18 second signal frequency, the IC3 division of the 14 states the following table. From the IC3 of the Q5, Q6, Q10, Q12, Q14 data output out 128s, 256s, 4096s, 16384s, 65536s sub-frequency signal, by VD3 ~ VD7, R3, R4 and the start button and the gate circuit consisting of AN by adding 86400s the 24h time-reset signal, and sent to the IC3 by R4 reset input R (11 feet), when all 5 output is high, the sum obtained by VD3 ~ VD7 24h time that the value of 86400s, when IC3 reset, all output is zero, so that time is 24h automatic cycle timing. This IC1 ~ IC3, VD1 ~ VD7 and peripheral components VT, R1 ~ R4, C1 ~ C3 cycle timing circuit composed of 24h. The role of R4 is to avoid damage when pressing the AN connection with VD3 ~ VD7 IC3 data door. As the clock generated by the quartz watch integrated circuit, the timing error in the 3s at less than full compliance with lighting saver clock timing requirements, clock circuit can work without any debugging. IC4, IC5 two cascaded 4-bit magnitude comparator composed of 8-bit magnitude comparator, IC4 cascade input A, A0, A1 take the high potential, A2, A3 then IC3, IC5 data input termination IC3's Q11 A ~ Q14 output frequency, timing circuits cycle from 24h to remove 2048s (34min8s) ~ 85488s (23h51min28s) interval for the 2048s of 64 6 time data as input data A, IC4 of the A0, A1, B0, B1 then high level, taken from the DIP switch BCD BCD 4-bit data to the data input of IC4 B2, B3, and IC5 of B0, B1-side, as IC4, IC5 data B, the 4-bit data, IC5 of the B2 high voltage termination 83 termination of low potential. This can be set by DIP switch BCD time data 10 of a clock sent with the time clock data (the specific digital values in Table) compared.

A less than the BCD timing data when the DIP switch to set the time when the data B, IC5 output low of 5 feet, IC6 was electric conduction is triggered, the relay CJ1, CJ2 light photo light absorption. Conversely, when data A is greater than the data B, IC5 output of 5 feet high, IC6 no trigger voltage shutdown, CJ1, CJ2 release, lights off. IC4, IC5 of the input data that Q9 ~ Q14 seconds from zero to more than BCD time code switch time data set should be lit at night time, the data A is greater than B BCD time data set has been reset to 24h cycle So far this time when the lights during the day time. 24h cycle timing circuit which should be the starting point on the dark, when lights need to light up, rather than the middle of the night Beijing time zero. BCD DIP according to the figure selected data, press the start button in Beijing 17:30:00 AN, that is locked in Beijing 17:30:00 a starting point for the cycle time. In Beijing the next day 07:09:12 GMT 17:30:00 ~ bright lights, Beijing 07:09:13 ~ 17:29:59 light does not shine. The start time of 24h cycle timer adjusted by the way, saving a set of lights to determine the starting time of the circuit, only a set of lights-out time to estimate the circuit, it can omit the time display circuit, so that the circuit is very simple, but also reduces clock accuracy requirements of travel time, production cost is also reduced accordingly.
IC4, IC5 value cascade composed of the 8-bit comparator, if the BCD with two DIP switch, and A, B to use all of the input data, can be composed of 256 points the shortest time interval 512s of the circuit. Costs increased by only one BCD switch, composed of time intervals can be shorter, finer division of the circuit. However, BCD has been basically met only one energy-saving lighting control needs, and more simple to use some. The circuit is the shortest time time 9h6min8s (the shortest summer night from about 19:40 to 5:10 the next day, no more than 9.5h), up to 14h13min20s (the longest winter night from about 17:00 to 7:00 am 14h). 34min8s interval points to 10 grades, with the BCD DIP switch numbers 0 to 9 in 10 with one to one (such as the former table.) Power supply circuit from the transformer B will be reduced to 220V 6V, by VD8 ~ VD11, C4 rectifier filter, after IC7 stable regulated output voltage of 3.6V. In the back-up battery anode and ground potential indirectly IC7 a diode VD12. 24h cycle timing circuit will be negative to the battery's negative terminal, the comparator circuit and the other received IC7 negative extreme negative extreme. When there is power, 3.6V suspended by VD12 charge the battery while the normal power supply to the circuit. When a power failure, the battery part of the 24h cycle timing circuit power supply to ensure accurate timing, correct. The role of isolation by VD12 not to other circuitry to ensure that the battery back-up use of time longer. Timing circuit power consumption of about a few microamps, with button-type lithium battery 3V time circuit can work continuously more than 3 months.