Abstract : This paper introduces the characteristics of the chip , AMD Am29LV160D , and WISHBONE bus made a brief , detailed description of the FLASH memory and the WISHBONE bus hardware interface design and the Verilog HDL source code section . Keywords : Flash ; Interface ; WISHBONE; FPGA Introduction As semiconductor process technology , IC designers have been able to microprocessors, analog IP core , IP core and the memory number (or off-chip memory control interface) integrated on a single chip , that SoC chip . System on Chip (SoC) data recording needs of low power, high-capacity , fast write cycles of memory .

Common media are: Dynamic memory (DRAM), static memory (SRAM) and flash memory (FLASH MEMORY). Large capacity DRAM , but the need to constantly refresh to maintain data , the microprocessor will occupy the time , while increasing power consumption ; SRAM does not have to dynamically refreshed , but the price is too expensive , and power followed by the same DRAM data can not be saved . FLASH MEMORY is a UV- erasable EPROM and both electrically erasable programmable read-only memory (EEPROM) advantages of the two new non-volatile memory . Because it available online for electrically erasable and programmable chip can be independently erased each district at least one million times more, and thus the need to periodically modify the code and data storage applications tables , and as a high-density Nonvolatile FLASH data storage media is the ideal device selection .

In our design system, the processor is Openrisc1200, FLASH is used by AMD and Fujitsu 's Am29LV160D chips . Using FPGA to achieve interface, as Openrisc1200 (OR1200) by WISHBONE bus, so the interface with the portability of this design . Am29LV160D chip features Am29LV160D is a 3.0V power supply using only read and write flash memory . The device provides a 70ns, 90ns, 120ns read time , high-speed microprocessors without wait states inserted for speed matching . .To eliminate bus competition , the chip into the Chip Enable (CE #), write enable (WE #) and output enable (OE #) control port . The chip block structure , making it ideal for high density code or data stored in low power systems.  low power consumption Work in the 5MHz , the current typical : Sleep mode current is 200nA; Standby mode current is 200nA; Read data to 9mA; Programming / erase mode current is 20mA. ? flexible block structure A 16KB, two 8KB, one 32KB, and 64KB block 31 ( byte mode) ; An 8KB, 2 4 KB, a 16 KB, 32 KB blocks and 31 ( word mode) ; Support for the chip erase ; Complex block protection.  The internal embedding algorithm Erase algorithm automatically pre- embedded within the programming and erase the entire chip or any combination of block ; Embedded algorithm within the given address automatically write data chip and its verification . Compatible with JEDEC standards. The hardware RESET Reset and Ready / Busy pin rewritable queries ? to continue with the erase suspend and erase functions About WISHBONE Bus WISHBONE bus specification is a system on chip interconnect IP core architecture . IP core which defines a logical interface between the public and reduce the difficulty of integrating the system components to improve the reusability of system components , reliability and portability , speed up the pace of product market . WISHBONE bus specifications can be used for soft-core , solid core and hard core , on the target hardware development tools and no special requirements , and almost compatible with all integrated tools can be used to achieve a variety of hardware description language . Flexibility is another advantage WISHBONE bus .

As the various types of IP core , during which there is no a unified indirectly . To meet the needs of different systems , WISHBONE bus provides four different IP core interconnection methods : Point to point (point-to-point), for both IP core direct interconnection; Data flow (data flow), for multiple serial data between the IP core concurrent transmission; Shared bus (shared bus) ( see Figure 1) , multiple IP core sharing a bus; Crossbar switch (crossbar switch), multiple simultaneous connections from the main components, increase system throughput . FLASH interface design As OR1200 WISHBONE shared bus is used , the address line 32 , data lines for 32-bit . Design will be low and FLASH used to link the degree of design and interface, 16 -bit . Block diagram shown in Figure 2 . Some logical interface using FPGA to achieve . System used Xilinx 's latest 90nm process manufacturing field programmable gate array chip, Spartan-3 to implement the interface design , use of programmable features of its brought simplify circuit design and debugging flexibility. FLASH read interface design The interface allows single-cycle read and read function block , sequential part and WISHBONE compatible . FLASH as the maximum time period used for at least 90ns, so only work in the bus clock frequency of 10MHz the following ACK_O port can directly associated with the STB_I port .When the MASTER ( instruction CACHE) issued a block of time signals , it will send a LOCK_O = VIH signal to the bus arbiter , the bus can be requested to provide uninterrupted bus . Its SLAVE (FLASH joints ) control signal is: WE_I = VIL, CYC_I = VIH, STB_I = VIH, BYTE = VIH When the MASTER end of the block reading signals can be sent STB_O = VIL . Part of its output interface shown in Figure 3 .

The output interface module source code is as follows : module WBOPRT16 (CLK_I, RST_I, WE_I, STB_I, ACK_O, DQ_I, DAT_O); / / WISHBONE SLAVE interface --- Input CLK_I, RST_I, WE_I, STB_I; --- Output ACK_O; --- Output [15:0] DAT_O; ---// Non-WISHBONE interface --- Input [15:0] DQ_I; --- Reg [15:0] DAT_O; --- Always @ (posedge CLK_I or negedge RST_I) --- Begin: label_A --- If (! RST_I) --- DAT_O <= 16'b0; / / asynchronous reset --- Else if ((STB_I &! WE_I) == 'b1) --- DAT_O <= DQ_I; --- Else --- DAT_O <= DAT_O; --- End --- Assign ACK_O = STB_I; --- Endmodule