Communication with the development trend of the receiver is required to signal the receiver has just entered the channel when the sampling signal , and equipped with precision testing apparatus , which has to lean to achieve this objective high-speed analog -digital converter to achieve . National Semiconductor is a devaluation of the ADC081000 chip analog input bandwidth of up to 1.8 GHz 8-bit 1GSPS analog -digital converter , which uses 0.18 micron (mm) of complementary metal oxide semiconductor (CMOS) process technology. A brief outline of the structure and principles of action , and a more detailed description of the above-mentioned process in the action play any important role . Looking at the current market , most of the high-speed analog -digital converters are used bipolar complementary metal oxide semiconductor (BiCMOS) process technology , so ADC081000 a chip is the first fully manufactured using CMOS technology analog -digital converter products . Since bipolar transistors than CMOS transistors with low offset voltage , while the gain is higher , so engineers have always liked using bipolar chip design front-end analog -digital converter , sample and hold amplifier , etc. For example, signal conditioning circuit . The need to support high frequency operation of the system , the bipolar chips in particular, welcomed by the engineers . However, the shortcomings of bipolar chips need high -powered , its power than similar chips using CMOS technology, great . ADC081000 chip about the actual power consumption is only 1W . In contrast, the market 's lowest power BiCMOS analog -digital converter is more than 3W of power consumption . How to install the radiator can be a lot of heat so all the distribution ? This is a matter of great headache. ADC081000 chip not only performance, but also with communications systems and high-performance test instruments required for the dynamic specification , which provides more than 7 effective bits (ENOB), far exceeding the Nyquist (nyquist) requirements. Structure and operation principle High-speed analog -digital converter with a variety of structures to choose from, which the flash , pipelined , or folding / interpolating three kinds of the most popular . With flash and folding / interpolating the structure of digital CMOS process allows greater flexibility in play . Folding ADC has the advantage of fast and needed more than the flash device ADC less . Interpolating analog -digital converter , is only a very small amount of input amplifier , and the lower the required input capacitance . We know the folding / interpolating structure is the integration of these two technologies , the advantage of smaller die size , power consumption low, then high dynamic performance , the chip will use this structure ADC081000 Figure 1 is shown a block diagram of the chip . 1GSPS speed to provide sufficient time to time : To ADC081000 such high-speed , high-performance integrated circuits for the clock signal that they must not be required to accompany any noise , to ensure that the external clock would not be unwelcome noise into the system and affect overall system dynamic performance. ADC081000 chip clock needed to be a low phase noise (low jitter ) clock , and must be able to gigahertz (GHz) frequency of operation above . Although the traditional crystal oscillators provide low jitter clock signal , but the market only a few oscillation frequency of the quartz oscillator to provide more than a few hundred megahertz (MHz) clock signal . In order to ensure that the oscillation frequency and low phase noise to meet the requirements , we can use high-frequency voltage-controlled oscillator (VCO), phase-locked loop (PLL) and the quartz oscillator , in accordance with the design shown in Figure 2 will be the integrated one , which Is the best way . National Semiconductor recently introduced the industry's first high-performance PLL and VCO combo solution, to further strengthen its lineup of wireless communications products . LMX25XX chip series has the advantage that the center of its RF output frequency of 800MHz to 1.4GHz set in between . This series chip low phase noise , to ensure that the jitter will not affect the ADC081000 chip signal to noise ratio (SNR). Design of high-speed analog -digital converter system design engineers know will reduce the clock jitter analog -digital converter signal to noise ratio . The input signal to 500MHz for example , 3ps rms jitter signal to noise ratio can be reduced to the maximum limit of 40.5dB, which is calculated as follows : ADC081000 chip internally generated sampling clock jitter to be minimal , the effects are basically negligible. Clock design with great care, the design must also consider the implementation of practical application , this can give full play to ADC081000 chip performance. But is not involved in a variety of techniques within the scope of this article . One thing worth mentioning , the clock 's design is extremely important , we propose the circuit in Figure 2 . For further inquiries about the information can be found in ADC081000 chip data sheet. The face of 1Gbps of data transmission speed per second , we do? In order to facilitate the capture the output data , ADC081000 chips with low-voltage differential signaling (LVDS) and CMOS are two modes of operation . ( below LVDS technology will be a brief principle of operation ) . As long as we will be logic high or logic low connection pin 1, will select the required mode . LVDS mode of operation using the internal 1:2 multiplexer output bus distributor is responsible for both feed and reduce the output data rate to only half the sampling rate . Using CMOS mode operation , the internal 1:4 multiplexer output bus distributor is responsible for the four feed , as well as the output data rate down to only a quarter of the sampling rate . The data on the bus while interlacing , so that each bus to each of 500MSPS and the output data rate of 250MSPS , so total data output rate of up to 1GSPS. LVDS or CMOS regardless of the mode operation , the system must provide one or more data transfer process and output the output clock synchronization in order to simplify the data capture process . Operation of the process should pay attention All the high-performance components in the application process are functioning as a whole , not a one of the independent individual , it is very important , so an application , the op amp and the converter will affect the overall running good or bad Action. Is widely used digital oscilloscope , communications , semiconductor and computer industries such as system design and test engineers often use digital oscilloscope . Such instruments rely on a high sampling rate, high input bandwidth analog -digital converter . In fact, this is the heart of the whole instrument , as the oscilloscope input bandwidth and sampling rate is entirely analog -digital converter front-end decision . For example, the input bandwidth of 1.5GHz of 1 GSPS oscilloscope must meet these specifications using analog -digital converter . Measuring instruments must have enough bandwidth signal can be accurately measured . Measurement signal, the analog bandwidth oscilloscope must be sufficient to support the high-frequency part of the signal . For example, the oscilloscope must be able to provide input bandwidth of 100MHz and above , can be measured without filter 100MHz sine wave . Because some high-frequency square wave into wave frequency many times higher than the fundamental frequency , so the oscilloscope to provide far more than 100MHz input bandwidth of 100MHz square wave can be measured . Sample if insufficient bandwidth , it will lose some of the original signal 's frequency and amplitude . This square wave will not be able to show the shape of a square wave in oscilloscope screen. Sampling rate analog -digital converter analog signal into digital signal rate . The higher the sampling rate , high-frequency signal can be recovered more accurately . For example, 1GSPS signal sampling rate of recovery of 100MHz to 500MHz sampling rate of recovery than the same signal closer to the original signal . Therefore, high sampling rates such as ADC081000 , high input bandwidth and low error rate (BER) of digital -analog converter is ideal for high-frequency digital signal converter, ideal for system design and testing . Manufacturers can use this analog -digital converter developed low-cost , high-performance test equipment. Another typical application is a digital radio receiver. For years digital conversion technology is developing rapidly, so the receiver could be more extensive use of digital integrated circuits . Of course, the more the receiver's digital circuit near the antenna , the more advantages can play receiver . So some people believe that the analog -digital converter placed in the output of the RF system for direct RF sampling . This design seems preferable , but here another problem arise , we have to be considered. In order to suppress unwanted pre- band signal , and analog -digital converter to meet the required frequency range , the received signal is input before the analog -digital converter must be filtered , and to receive automatic gain control . So many digital receiver with a compromise , first the output level will be the first and second intermediate frequency analog signals into digital signals , so that band signal into the analog -digital converter has not yet accepted first before filtering , but also to ensure that part of the signal Not enter the analog -digital converter in the simulation before the first class to accept automatic gain control , to minimize in-band signal over drive the analog -digital converter , analog -digital converter during the signal can be achieved before the maximum signal gain . In addition, the use of a frequency sampling and digital receiver technology, will be without any additional IF stage , such as mixers, filters and amplifiers , will help reduce costs, and system design engineers to the use of a programmable digital filter to replace the fixed analog filtering Devices can give full play to the design flexibility. As the ADC081000 chip 1.8GHz 3dB bandwidth available , so most suitable for direct sampling of RF or IF . The converter chip can significantly reduce the required number of expensive analog chips , help reduce overall system cost . In addition , even with much much higher requirement?????frequency operation , the total harmonic distortion can be maintained at a relatively low level , so that sampling rate must be less than the system such as satellite receiving system can also be the normal implementation.