Abstract: This paper presents the application of the TMS320C6000 DSP McBSP I2C bus interface protocol to achieve the method , so that you can access other needs of the DSP I2C bus configuration of smart devices , the system structure is simple , easy hardware design , resource consumption and small . Keyword: I2C Bus GPIO McBSP DSP 1 Introduction TI 's TMS320C6000 [1,2] series is a high performance DSP, can be widely used XDSL, wireless base stations , digital image processing and so on . During digital image processing, usually video decoder , such as SAA7111A analog video front-end like , and most of the video decoder is initialized by the two lines are usually I2C bus interface , but now most of DSP and MCU No I2C bus interface , in which case we can apply the two general-purpose IO lines, through the software to simulate the I2C bus protocol , and then complete the I2C bus interface . In the TMS320C6000 usually has two or more multi-channel buffered serial interface McBSP, McBSP serial interface can not only preparation of the preparation can also be an independent input into the universal (GPI), output (GPO) and the input and output ports (GPIO). I2C [3] is a two-way serial bus data line (SDA) and serial clock line (SCL) two signal lines connected to the bus transfer information between devices . Bus can be set for each device a unique address, and then set the functions according to information sent or received . As well as transmitter and receiver and, in the implementation of data transfer , the bus device can be set by the main controller and the controller . Usually started by the master data transfer bus , and generates data clock signals required . Was the address of the other devices are subject to controller , which means that the bus can connect multiple devices with control bus . I2C bus data transfer rate of 100kbit / s, fast mode up to 400kbit / s. Devices connected to the bus number is limited only by 400pF bus capacitance limit. Meanwhile, in order to avoid confusion in the bus signals , required to connect to the bus output of the device must be open collector or open-drain in order to generate " line and "function . I2C bus SDA and SCL lines are bi-directional transmission line , which can be connected through a resistor to positive supply -side , when the bus is idle , the two lines are high . 2 Hardware Design I2C bus hardware design is very easy , simply connect SDA and SCL can be , in the I2C bus allows only one master , the rest are by the controller . When the number of nodes greater than the limit 400pF , you can drive by bus to the bus as 82B715 to expand . Connection shown in Figure 1 3 Software Design 3.1 McBSP Configuration I2C Bus applications McBSP two pins , the first feature to be disabled McBSP McBSP pins configured as GPI, GPO, GPIO. In this paper, McBSP0 of CLKX0 as I2C bus SCL, FSX0 as the I2C bus SDA, McBSP of DX, DR, usually can not be configured to I2C of the SDA, as SDA is a bidirectional, and DX, DR can only be made into a single input or Output . Configuration code is as follows: McBSP0_SPCR = 0x00000000; / / McBSP0 send and receive reset McBSP0_PCR = 0x00003F00; / / McBSP0 all the pins are configured as GPIO, CLKX0 and FSX0 the output SCL for the host is always output, so it 's direction is constant , SCL should be 0,1 as the interface clock output , in order to achieve this function we define a macro (MACROS): SET_SCLHI () SET_SCLLO () # Define Set_SCLHi () McBSP0_SPSA = PCR; McBSP0_SPSA | = 0x00000002 # Define Set_SCLLo () McBSP0_SPSA = PCR; McBSP0_SPSA & = 0Xfffffffd I2C bus data line SDA while the writing of the input , when reading the output . In order to change the direction of SDA can be defined Set_SDADirOut () Set_SDADirIn () # Define Set_SDADirOut () McBSP0_SPSA = PCR; McBSP0_SPSA | = 0x00000800 # Define Set_SDADirIn () McBSP0_SPSA = PCR; McBSP0_SPSA & = 0xFFFFF7FF SDA should be in accordance with the data bits 0,1 to change the definition to output 1,0 Set_SDAHi () Set_SDALo () # Define Set_SDAHi () McBSP0_SPSA = PCR; McBSP0_SPSA | = 0x00000008 # Define Set_SDALo () McBSP0_SPSA = PCR; McBSP0_SPSA & = 0xFFFFFFF7 After the definition of good can simulate I2C bus protocol for transmission , such as the I2C bus interface SAA7111A is used to initialize SAA7111A used , SCL the frequency can be from 0 to 400KHZ, to control the SCL frequency can be applied to DSP- TIMER0 to control . When the CPU time for the 100MHZ : TCR = 0x00000010; / / stop TIMER0 and TDDR = 0 PRD = 6249; / / TIMER0 rate = CPU-Frequency / (PDR +1) = 100MHz/6250 = 16kHz ... TCR & = 0xFFFFFFEF; / / start TIMER0 3.2 I2C Bus Protocol Programming 3.2.1 I2C bus protocol read and write data flow programming For I2C -bus communication, we use each data stream 4 (FRAMES), in order to minimize delay and noise , four for each data stream to ensure the SDA will not change at the edge of the SCL , only allows data changes in the FRAME0, read only FRAME2. Figure 2 I2C bus, write the following procedure void I2CWrite (unsigned int WriteBit) {Set_SDADirOut (); / / set SDA as output switch (FrameCount) { case (0): / / start frame Set_SCLLo (); / / SCL 0 if (WriteBit == 0) / / SDA = WriteBit Set_SDALo (); else Set_SDAHi (); break; case (3): / / No. 4 Set_SCLLo (); / / break; default: / / in frame 2,3 Set_SCLHi (); / / SCL 1 } FrameCount + = 1; / / frame count if (FrameCount> 3) { FrameCount = 0; BitIndex = (BitIndex>> 1);} / / prepare to send next bit } I2C bus read and write procedure program is very similar , just change the SDA as input. 3.2.2 I2C bus start bit and stop bit of programming I2C bus start bit and stop bits have three generation transmission in the I2C bus , only when the bus is idle (SCL line and SDA lines are high ), the data transfer can begin , any device on the bus at this time Both can control the bus . Which is high when the SCL line and SDA line changes from high to low for the start conditions; and when the SCL line is high and the SDA line from low to high end when the conditions . Figure 3 Start bit : void I2CSTA () {/ / I2C start bit Set_SDADirOut (); / / define SDA as output switch (FrameCount) { case (1): / / No. 2 Set_SCLHi (); Set_SDALo (); break; case (2): / / third frame Set_SCLLo (); Set_SDALo (); break; default: / / the first frame Set_SCLHi (); Set_SDAHi (); } FrameCount + = 1; / / frame count if (FrameCount> 2) { FrameCount = 0; BitIndex = 0x0080;} / / define the lower 8 bits } Stop bit of programming only in accordance with the above mentioned will be SCL line is high and the SDA line from low to high you can . 3.2.3 I2C Bus data format Initiation controlled device address read and write control bit 0 / 1 response bit data acknowledge bit ... stop bit I2C bus data transfer format [3 ] in Figure 4 . The first part of the start signal for data transmission , data transmission that starts here ; second part, by the controller address , which is used to select the transmission of data by the controller ; The third part is read / write control bit for Directed by the controller 's work , 0 for write , 1 for reading ; fourth part is to be selected by the master controller to the master return confirmation signal ; The fifth part is the transmission of data , each Transmit a byte of data , require a response bit ; sixth part is the end of data transmission signals . I2C bus interface, each with a controlled device has a unique fixed address , when master sends data , I2C bus controlled devices are attached to master issued , in the initial 8-bit signal Address information to compare with their own addresses , if the two are the same, that the controlled device is selected , and then follow the read / write bit of regulations to receive or send data . The above procedures can be applied in accordance with the I2C -bus data format for data transfer. 4 Conclusion Application of DSP 's McBSP to design the I2C bus interface , hardware interface is simple, easy debugging , and hardware cost savings , this method has been used in DSP- based image matching machine , the method is feasible and reliable .