[Abstract] This paper introduces the features and performance MAX813L working principle, and gave the 51 interference in the SCM system application example, details the hardware connection circuit and the corresponding anti-jamming software programming skills.
[Key words] MAX813L; interference; SCM
In recent years, single chip with its small size, reasonable price, and other unique advantages for control, in a variety of industrial control, instrumentation, equipment, products, automation and intelligence gained a wide range of applications. At the same time, microcomputer application system reliability become increasingly important topic of concern. There are many factors affect the reliability, such as the composition itself, the reliability of the system components, the system itself, the coupling between the various parts of factors. The system includes anti-jamming performance is an important indicator of system reliability.
Based on the analysis based on the principle of MAX813L, with practice gives the MCU system in 51 examples of specific immunity. Described in detail the working principle of the hardware circuit and the corresponding programming system program interference.
1 MAX813L chip and its working principle
1.1 Chip characteristics
* Power, power down and power supply voltage drop in case of reset output, the reset pulse width is typically 200 ms.
* Independent watchdog output, if the watchdog input has not been triggered within 1.6 s, the output will go high.
· 1.25 V threshold detector for power failure alarm, low battery detection or +5 V power supply other than monitoring.
* Active-low manual reset input.
* 8-pin DIP package.
1.2 MAX813L pin and function
1.2.1 MAX813L chip pinout shown in Figure 1-1

1.2.2 and working principle of the pin function
(1) Manual reset input ()
When the low-side input to maintain more than 140 ms, MAX813L reset signal to the output. The input requirements of the minimum input pulse width can effectively eliminate the switch jitter.With TTL / CMOS compatible.
(2) Power supply terminal (VCC): +5 V power supply connected.
(3) Power ground (GND): 0 V reference level access.
(4) Power failure input (PFI)
When the terminal when the input voltage drops below 1.25 V, 5-pin output signal from high to low.
(5) power failure output ()
Power is normal, remain high, low or power-down supply voltage changes, the output from the high to low.
(6) watchdog signal input (WDI)
Normal operation procedures must be less than 1.6 s within the time interval to send a pulse signal input to clear the watchdog timer chip. If more than 1.6 s can not receive the pulse signal input, the internal timer, 8 pin from the high to low.
(7) Reset signal output (RST)
On power reset automatically generated 200 ms pulse; manual reset input low side, the client also generates a reset signal output.
(8) watchdog signal output ()
Output remains high during normal operation, the watchdog output, the end of the output signal from the high to low.

2 Circuit Design
2.1 The basic principle
Most of the industrial environment based on the interference in the form of narrow pulses, and ultimately result in the majority of computer system failure phenomenon as a "crash." The reason is that in the execution of a CPU instruction, the impact of interference, so that its operation code or address code is changed, resulting in errors in the instructions. At this time, CPU perform random spelling instruction, even as the operation operand code execution, causes the program to "run off" or enter "death cycle." To make this kind of "running out" or enter the "death cycle" of the program to automatically recover and re-work, an effective approach is to use hardware "watchdog" technology. With a watchdog to monitor the program. If the process is occurring "death", the watchdog reset signal to guide the microcontroller program to re-enter normal operation.

In addition, because many large industrial site into electrical equipment or the withdrawal of power grid operation, often resulting in the power system voltage instability, when the supply voltage drops or power failure will cause major loss of data, the system can not function properly. If you try to power supply voltage down to a certain limit before the MCU quickly to preserve important data, it will minimize losses.
MCU Power-down mode circuit diagram shown in Figure 2-1: When the PD is set to 1, the active power-down mode, time= 0, and the NAND gate output is low, the clock generator stops working, the microcontroller are stopped all the running, only the on-chip RAM and SFR data is stored. In the SCM system can be attached by means of some external circuitry to monitor power supply voltage, and power failure promptly notify the microcontroller (such as by raisingInterrupt to achieve) Quick save important data, and disconnect the power supply external devices, the power consumption of the entire application down to a minimum. When the power is restored, the abolition of power-down mode, by resetting the MCU, the system re-work.

2.2 The hardware circuit
Figure 2-2 shows the MAX813L in the SCM system in the typical application circuit diagram. This circuit can achieve power, instantaneous power-down and run a "crash" any time when the automatic reset and manual reset; and can be monitored in real-time power failure in order to save the data in a timely manner.
The clever use of the MAX813L circuit manual reset input. Once the program as long as the flight cause the program to run "crash"Side level from high to low, whenTo low 超过 140 ms, will cause MAX813L produce a reset pulse 200 ms. At the same time the watchdog timer to 0 and thePin becomes high. Can always use the manual reset button to reset MAX813L pulse, reset pulse generated due toRequired to maintain at least 140ms low end or more, it can effectively eliminate the switch jitter.
The circuit can be monitored in real-time power failure (power-down, voltage drop, etc.). Figure 2-2 R1 a termination without regulated DC power supply. Power is normal, to ensure that the voltage on R2 than 1.26 V, which is to ensure MAX813L the PFI input level higher than 1.26 V. When the power failure, PFI input level is lower than 1.25 V, the output of a power failureLevel from high to low, causing microcontrollerInterrupt, CPU interrupt, perform the appropriate interrupt service routine, protect data, disconnect the external electric circuit.

3 anti Programming
3.1 run " crash " and Countermeasures
The program runs normally, by the main program in less than 1.6 s time interval from the P1.7 terminal periodically the WDI to MAX813L sends a pulse signal input to clear the watchdog timer chip. For the order is:
RST-PRG: SETB P1.7
NOP
CLR P1.7
If more than 1.6 s can not receive the pulse signal input, the internal watchdog timer, 8 pin from the high to low. Cause MAX813L produce a reset pulse 200 ms. At the same time the watchdog timer to 0 and thePin becomes high.
Require attention is the completion of reset the MCU system, under the guidance of the PC pointer 0000H address the entire process from start initialization operation, which in many cases are not allowed (such as continuous process) , this must take the appropriate measures. First, the completion of the SCM system reset, the program should first determine a boot operation (cold start) or run the process, "crashed" after re-loading operation (hot start). Because under normal circumstances in both start mode, the system program before entering the main flow of work to be done often different. Such as cold start, the system initialization process program for system resources, often self-test and the peripheral devices will be set to the corresponding standby status. After the hot start is no longer on the system resources are often self-test, and should try to avoid modify the settings of various peripheral devices, but on the SCM system itself some of the resources necessary to set work. Second, in most cases, we can always put a continuous process to be unbundled, turn it into a separate sub-process (state) consisting of a continuous process. In the main program is running, timely save the corresponding state and parameters of the state. So that when the program runs a "crash" in MAX813L system reset and initialization under, it will first check the status of pre-stored parameters, and then based on this parameter determines the program flow. At the same time to save the state of the parameters in advance out of the system peripherals set to make the necessary restoration work and guide the process to continue running. Systems designed according to this thinking process flow chart shown in Figure 3-1.
Power failure and Countermeasures 3.2
When the power fails, causing microcontrollerInterrupt, CPU interrupt, perform the appropriate interrupt service routine, protect data, disconnect the external electric circuit. To do this, must beInterrupt priority (PX0) is set to the maximum, in particular, there are other interrupt system, and even more so. Set interrupt priority can be achieved through the interrupt priority registers IP, in addition to set the interrupt enable register IE's total allowable bit (EA) and the external interrupt 0 Interrupt (EX0). For the order is:

SETB IP. 0; set PX0 = 1
SETB IE. 7; setting EA = 1
SETB IE. 0; set EX0 = 1

The trigger mode interrupt source. If you choose to level-triggered, the interrupt must erase external auxiliary circuit, or can not interrupt the normal execution; If you choose to jump the trigger, whenWhen a negative transition end, CPU internal hardware IE automatically set the flag 0 , CPU interrupt through vector address when the interrupt service routine into the IE 0 by hardware to 0. Therefore, the above analysis, must be selected transition trigger. Trigger the timer control register TCON the IT 0 bits. For the order is:
SETB TCON. 0
Interrupt service routine design is continuous and reliable operation of the system is important. In the interrupt service program, first save important data to the on-chip RAM (standby power supply when power from the corresponding realization of the circuit not shown). Disconnect the peripheral equipment control signals, and finally the Power Control register PCON of the PD position 1 to activate power-down mode, the interrupt returns. Interrupt service routine to achieve the following (where R0 on behalf of the data stored in memory buffer The first address, DPTR representative of the data you want to save the buffer in external RAM, the first site, R1 on behalf of the amount of data bytes to be saved):
INT0: MOVX A, @ DPTR; save data
MOV @ R0, A
INC R0; memory buffer pointer by 1
INC DPTR; external memory buffer pointer 1
DJNZ R1, INT0; save all? Too much, and continue to save
SETB PCON. 1; active power-down mode
RET1

4 Conclusion
MAX813L clever use of the system chip, the microcontroller system to achieve the watchdog circuit, power failure monitoring circuit and manual and automatic reset circuit, the circuit compact design and reasonable. Interference with the procedures presented in this paper design, can be run effectively address the phenomenon of "death" phenomenon and the adverse effects of power failure. In our design of GaN semiconductor thin film growth process in real-time monitoring system, the actual operation shows: The design is reasonable, reliable operation, anti-interference ability, to the satisfaction of the results, and can be generalized to other SCM control system go.