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Maximum Mode 8086 System

  • In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground.
  • In this mode, the processor derives the status signal S2, S1, S0. Another chip called bus controller derives the control signal using this status information .
  • In the maximum mode, there may be more than one microprocessor in the system configuration.
  • The components in the system are same as in the minimum mode system.
  • The basic function of the bus controller chip IC8288, is to derive control signals like RD and WR ( for memory and I/O devices), DEN, DT/R, ALE etc. using the information by the processor on the status lines.
  • The bus controller chip has input lines S2, S1, S0 and CLK. These inputs to 8288 are driven by CPU.
  • It derives the outputs ALE, DEN, DT/R, MRDC, MWTC, AMWC, IORC, IOWC and AIOWC. The AEN, IOB and CEN pins are specially useful for multiprocessor systems.

  • AEN and IOB are generally grounded. CEN pin is usually tied to +5V. The significance of the MCE/PDEN output depends upon the status of the IOB pin.
  • If IOB is grounded, it acts as master cascade enable to control cascade 8259A, else it acts as peripheral data enable used in the multiple bus configurations.
  • INTA pin used to issue two interrupt acknowledge pulses to the interrupt controller or to an interrupting device.
  • IORC, IOWC are I/O read command and I/O write command signals respectively.
  • These signals enable an IO interface to read or write the data from or to the address port.
  • The MRDC, MWTC are memory read command and memory write command signals respectively and may be used as memory read or write signals.
  • All these command signals instructs the memory to accept or send data from or to the bus.
  • For both of these write command signals, the advanced signals namely AIOWC and AMWTC are available.
  • Here the only difference between in timing diagram between minimum mode and maximum mode is the status signals used and the available control and advanced command signals.
  • R0, S1, S2 are set at the beginning of bus cycle.8288 bus controller will output a pulse as on the ALE and apply a required signal to its DT / R pin during T1.
  • In T2, 8288 will set DEN=1 thus enabling transceivers, and for an input it will activate MRDC or IORC. These signals are activated until T4. For an output, the AMWC or AIOWC is activated from T2 to T4 and MWTC or IOWC is activated from T3 to T4.
  • The status bit S0 to S2 remains active until T3 and become passive during T3 and T4.
  • If reader input is not activated before T3, wait state will be inserted between T3 and T4.