Abstract: PCI9656 is a PLX Introduces 64-bit, 66MHz PCI-interface circuit. Flexible connectivity and high-performance I / O accelerator characteristics, for PCI, Compact PCI and embedded host designs. This paper describes PCI9656 functions, characteristics and application, give specific examples, while noting that the application should pay attention to the problem.

  Introduction
  PCI bus is the most extensive and most popular form of high-speed synchronous bus with 32bit bus width, bus clock frequency of 0 ~ 33MHz, the maximum transmission rate of up to 132Mbyte / s, and can be extended to 64-bit, 66MHz frequency. The bus has a maximum data transfer rate up to 528Mb / s, much larger than the ISA bus 5Mbyte / s speed. PCI bus and CPU has nothing to do has nothing to do with the clock frequency, it can be applied to various platforms, supports multiple processors and concurrent operation.
PCI bus protocol is more complex, the interface circuit so it is also more difficult to implement. It not only has strict timing requirements simultaneously, and that the use and automatic configuration to achieve plug, PCI interface, but also has many configuration registers. For the average designer, in order to shorten the development cycle, there is no need to design all of the interface logic, as long as the use of universal PCI interface circuit can be very good for development and design, thus greatly reducing the difficulty of the work.
Currently, the industry-based 32-bit PCI bus interface chip is used frequently in the company's S59xx AMCC's family and the PLX PLX series. The existing ordinary computer companies have 32-bit architecture, the system memory addressability has reached 4GB, therefore, a 32-bit PCI bus can not meet the increasingly large data processing needs. In view of the Itanium processor, Intel introduced 32-bit jump directly from 64-bit, so developers 64-bit PCI bus-based interface device is very important. The following describes a 64-bit PLX's PCI9656 PCI bus interface circuit type.

1 PCI9656 Overview

PLX PCI9656 is the adapter card for the expansion of the company launched to provide high-performance PCI bus target mixed-mode interface circuit, the interface circuit for the adapter card provides high-performance 64-bit PCI bus, a small target interface. PCI9656 internal structure of the block diagram shown in Figure 1. Its main features are as follows:
comply with PCI V 2.2 protocol support for 64-bit, 66MHz PCI bus clock, especially for the PCI bus peripheral product development.
the use of PLX data pipeline architecture (Data Pipe Architecture) technology, is equipped with DMA engines, programmable Direct Master or Direct Slave data transfer modes and PCI messaging functions.
devices with PCI first sentence, the external master can support 7.
can be two local bus interrupt signals LINTi and LINTo generate a PCI interrupt INTA.
local clock and PCI clock is asynchronous, allowing independent of the PCI local bus clock.
support for multiplexing and non-multiplexed 8-bit, 16-bit and 32-bit 66MHz local bus clock.
directly generate all the control, address and data signals to drive the PCI bus, no additional driver circuitry.
can be through message management system I / O, and provides 2 ways to select, one by the mailbox registers and doorbell registers, the second is provided by the I2O interface.
Register PCI9054 register compatible, can easily be 32-bit PCI bus-based 64-bit PCI bus-based software migration.

2 PCI9656 functions

PCI9656 available to non-PCI devices and PCI bus to provide data access. Here are the specific operation functions.

2.1 Initialization

When the power is, PCI bus RST signal PCI9656 internal registers set to default values, while, PCI9656 output of the local reset signal (LRESET) and check the EEPROM is present. If the system is equipped with EEPROM and the EEPROM of the first 16 bytes of non-empty, the PCI9656 will be set according to the contents of the internal EEPROM registers, or set to default values.
2.2 Reset
PCI bus RST signal is valid, the PCI9656 will be reset at the same time, the output LRESET local reset signal. Other PCI bus master devices can also set the software reset bits in the register to be reset to the PCI9656, but the master device can only access the configuration registers and can not access the local bus. Therefore, PCI9656 company has maintained this status until the PCI master device reset clear the software reset bit.
2.3 serial memory interface (EEPROM)
After reset, PCI9656 will begin to read the serial EEPROM, START 0 for EEPROM exist. At this point, if the first word of the EEPROM (16bit) not as "all 1" (EEPROM is blank) is not as "all 0" (EEPROM does not exist), PCI9656 will use it for configuration. If START is 1, there is no EEPROM or EEPROM that is empty, PCI9656 by default configuration.

PCI9656 bus master can read and write the serial EEPROM, register bit [31,27-24] controls the PCI9656 to read and write bits of EEPROM. Will reload configuration register bit CNTRL [28] set a serial EEPROM can be used to reconfigure the PCI9656. EEPROM clock by the PCI bus clock frequency available.
2.4 Internal registers
PCI9656 provides a series of internal registers for the bus interface design to provide maximum flexibility. These registers are PCI configuration registers, local configuration registers, DMA registers, register and run-time message queue register.
Read and write operations on the PCI9656 registers the unit can be a byte, word, long word. PCI9656 memory access can be abrupt or non-sudden.
2.5 Direct Data Transfer Mode
PCI9656 supports PCI bus on the main processor on the local bus device for direct access. PCI9656 configuration registers