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RQ/GT Timings in Maximum Mode

The request/grant response sequence contains a series of three pulses. The request/grant pins are checked at each rising pulse of clock input.
When a request is detected and if the condition for HOLD request are satisfied, the processor issues a grant pulse over the RQ/GT pin immediately during T4 (current) or T1 (next) state.
When the requesting master receives this pulse, it accepts the control of the bus, it sends a release pulse to the processor using RQ/GT pin.

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RQ/GT Timings in Maximum Mode