1. One of the problem In the field of industrial control and measurement is one of the more commonly used network physical layer RS-485 communication interface which consists of industrial equipment network . This communication interface is very easy to form a control network of many devices . MCU from the current solution in the long-distance communication between the many programs of view , RS-485 bus communication mode as simple structure , low cost, communication and data transfer rates from the appropriate other characteristics have been widely used in instrumentation, intelligent Sensors distributed control , building control, monitoring alarm and other fields. RS485 bus , but there is adaptive , self- protection vulnerabilities and other shortcomings, such as not pay attention to the details of the deal , or even system failures often appear paralyzed and other communication failure , so RS-485 bus to improve reliability is essential . Figure 1RS485 communication interface schematic

2 hardware design issues need to be noticed

2.1 The basic principle of the circuit A node hardware design shown in Figure 1 , in the circuit, using a RS-485 interface chip SN75LBC184, it uses a single power supply Vcc, voltage range of +3 ~ +5.5 V can work properly. And ordinary compared to RS-485 chip , it not only the impact of anti- lightning and can withstand 8 kV of electrostatic discharge up to the impact of an integrated four -chip transient over-voltage protection control , can withstand up to 400 V transient voltage pulse . Therefore , it can significantly improve the reliability of the device to prevent lightning damage . Some environment is harsher on the site , connecting directly with the transmission line without any additional protection devices . The chip has a unique design , when the input open circuit , the output is high , it will ensure that the receiver inputs are open circuit failure of cable does not affect the normal operation of the system . In addition, its input impedance of RS485 standard input impedance of 2 times (= 24 kO), so you can connect the bus transceiver 64 . Limit the slope of chip design -driven, the output will not steep signal edges , so that the transmission line does not produce much of the high frequency components , so as to effectively curb the electromagnetic interference . In Figure 1, four in one of the optical coupler TLP521 to SCM and SN75LBC184 are completely without power , and enhancing the reliability of the work . Basic principle is : When the MCU P1.6 = 0 , the optical coupler light -emitting diode , phototransistor conduction , the output high voltage (+5 V), select the RS485 interface chip of the DE side , allowed to send . When the MCU P1.6 = 1 , the optocoupler LED does not light , phototransistor does not turn the output low voltage (0 V), select the RS485 interface chip of the RE side , allowed to receive . SN75LBC184 R- end ( receiver ) and the D -side ( transmitter ) and the similar principle .

2.2 RS-485 control terminal of the DE RS-485 bus, built in half-duplex communication system throughout the network at any one time only one node in sending state to send data to the bus , all other nodes must be in the receiving state . If there are two nodes or two or more nodes simultaneously send data to the bus , will lead to the data sender to send all failed . Thus, each node in the system hardware design, should first seek to avoid anomalies caused by the node to send data to the bus caused the bus data conflict . To MCS51 MCU series , for example, because when the system reset , I / O port are high output , if the I / O port directly with the RS-485 interface chip Driver Enable end DE connected to reset in the CPU DE is high during the making , so that the node is sending state . If there are other nodes on the bus at this time is sending data, the data transmission will be interrupted and failed , or even cause the entire bus of a node failure because of blocked traffic , thereby affecting the normal operation of the system . Taking into account the stability and reliability of communication in the design of each node should control RS485 bus interface chip designed to send pin DE -side anti- logic that control pin for the logic "1" , DE -side to " 0 " ; control pin to logic "0" when , DE -side to "1 . " In Figure 1, the CPU pins P1.6 DE via optoelectronic coupler drive side , so make Kongzhiyinjiao Jiu Ke Yi Wei Gao Huozheyichang reset O'clock to SN75LBC184 always in the receiving state , Conger from the hardware on Youxiaobimian node Yin exception Circumstances the impact of the whole system . This is the system laid the foundation for reliable communications . In addition , there is a watchdog circuit MAX813L, death can occur in the node loop or other failure, the automatic reset procedure , to hand over control of RS-485 bus . This would ensure that the system does not malfunction because of an exclusive bus node , resulting in paralysis of the entire system .

2.3 Design to avoid bus conflict When a node needs to use the bus when the bus in order to achieve reliable communication , where data needs to send the case first listening bus . In the hardware interface , the first RS-485 interface chip data receiver connected to the CPU after the RP pin interrupt pin INT0. In Figure 1 , INT0 is connected to the output of optocoupler . When there is data being transmitted on the bus when , SN75LBC184 data receiving end (R side ) showed changes in the high and low , falling edge of its CPU generated interrupts ( also can use query method) , to know whether the bus at this time is " busy " , that is, nodes on the bus if there is communication . If the "free" , you can get on the bus use permission , so that solves the bus conflict. On this basis , you can also define the priority of all messages , so that high priority messages to be sent in order to further improve the system in real time. Using this work , the system has no master , divided from the node , each node on the bus, the permissions are equal , thus effectively avoiding the heavy burden of individual Jiedian communication situation. Bus utilization and efficiency of the system of communication have been greatly improved , thus making real-time response of the system improved , and even if individual nodes in the system failure will not affect other nodes in the normal communication and work. This makes the system a " danger " dispersed , to some degree the work of enhancing the system reliability and stability .

2.4 RS-485 output circuit part of the design In Figure 1 , VD1 ~ VD4 as signal limiting diodes , the value of its regulator should ensure compliance with the RS-485 standard , VD1 and VD3 take 12 V, VD2 , and VD4 take 7 V, to ensure that the signal amplitude limited -7 ~ Between +12 V to further enhance the ability of anti- over voltage . Taking into account the special circumstances of lines (such as a node in the RS-485 chip is puncture short ) , to prevent extension of the communication bus in the other affected the signal output in SN75LBC184 the two 20 Ohm series resistors R1 and R2 This is not the machine 's hardware failure will affect the entire bus communication . Construction site in the application of systems engineering , due to a twisted pair communications carrier , its characteristic impedance of 120 Ohm or so , so circuit design, the RS485 network transmission line, the beginning and end should be the pick end of a 120 O matching resistance ( Figure 1 in R3), to reduce the reflected signal transmission lines .

2.5 system, power options For RS-485 by the microcomputer with the formation of the monitoring network , each node should be given priority by the independent power of the program , while the power cord can not be shared RS-485 signal lines share the same multi-core cable . RS-485 signal lines should use cross-sectional area of more than 0.75 mm2 twisted pair instead of a linear , and the use of linear power TL750L05 more appropriate than use the power switch . TL750L05 must have output capacitance , if there is no output capacitor , then the output voltage of sawtooth shape , saw the rising edge with the input voltage change, plus the output capacitor , it can restrain the phenomenon. 3 software programming SN75LBC184 when the receiving mode , A, B input , R is the output ; to send modalities , D as input , A, B as the output . When sending a change of direction , if the input does not change , then the output of a random state at this time until the first input state changes , the output state was determined . Clearly, by the way sent into the receiving mode , if A, B state before the change , R is low , starting in the first data bits , R is still low , CPU that no initiation time Until the first falling edge , CPU only started to receive the first data , which will result in receiving an error . Send form by the receiving means after the transfer , D before the change , if A and B between the low voltage , start sending the first data bits , A and B is still among the low-voltage , A, B pin no start Bit , it will also send the wrong result . Overcome the consequences of the program are: the host sends two consecutive synchronization words , words to include multiple simultaneous edge change ( such as 55H, 0AAH), and send it twice ( the first time may receive an error and ignored ) , the receiver receiving synchronization Words , you can transfer data , and to ensure proper communication . In order to reliably work in RS485 bus switch state when the appropriate time delay , and then send and receive data . Specifically, the data sent in the state, the first control terminal set to "1" , the time delay of about 0.5 ms , and then send the valid data , the data sent after the delay and then 0.5 ms, the control -side set "0 . " This deal will switch state when the bus , a stable working process.