Abstract: SCAN90CP02 is National Semiconductor's new high-speed LVDS crosspoint switch, with the pre-enhancement can be applied to the backplane and high-loss cable connections to increase drive capability. Described in detail the function of the circuit, structure and configuration, and gives its application methods.
Introduction
Low Voltage Differential Signaling LVDS (Low Voltage Differential Signaling) is a high-speed, low voltage, low power, low noise general purpose I / O interface standards. This signal transmission with very small amplitude (typically 350mV), through a pair of parallel PCB traces or balanced cables to transmit data. This is parallel to the differential signal line current and voltage amplitude contrast, while the noise coupling to the two signal lines. As a result of differential input mode, input signal only on the difference between two signals, which may be out of common-mode interference suppression. In addition, the two differential signal lines in close proximity, the current transfer in the opposite direction, the magnetic fields cancel each other out, the electric field coupling, which compared with the single wire transmission, electromagnetic radiation is much smaller.
LVDS interface devices and has been widely used in field-programmable gate array (FPGA), application specific integrated circuit (ASIC), using the system successfully achieved LVDS high-speed interconnect. Then, not all of the LVDS I / O interface has a good performance. For example, some ASIC or FPGA's LVDS I / O devices may not like the standard of LVDS I / O board as suitable for driving differential PCB traces (trace). The PCB board layout problems and even lead to well-designed standard components of signal transmission quality deterioration. When using ASIC or FPGA core components such as a system, sometimes the device can be placed as close to the connector, this change will cause the trace lines, reflecting increases, loss increases. In order to eliminate interconnection problems, National Semiconductor has introduced a series of compact buffer. Paper will be its high-speed LVDS crosspoint switch SCAN90CP02 the function and application are introduced.

1 SCAN90CP02 Introduction
SCAN90CP02 type of circuit is the National Semiconductor Corporation introduced 1.5Gb / s in the 2x2 low-voltage differential signaling Analog Crosspoint Switches (crosspoint switch). And through its high-speed data path (flow-through) pin allows the internal circuitry to minimize jitter. When the signal at the expense of the backplane and cable transmission, and its configurable pre-emphasis function (0/25/50/100% available) can overcome the external ISI (Inter Symbol Interference, ISI) jitter. The differential input can be connected to LVDS and Bus LVDS signals can also be common mode logic (CML) and low-voltage positive emitter coupled logic (LVPCL) and other connected signal level. SCAN90CP02 to use non-blocking cross-point structure, can be configured for 1:2 clock or data distributor, 2:1 redundant multiplexers, cross-functional and used for signal enhancement and short-term hidden double buffer. Figure 1 is an internal block diagram SCAN90CP02.
SCAN90CP02 integrated IEEE 1149.1 (JTAG) and 1149.6 test input circuit TAP (Test Access Port) to support single-ended LVTTL / CMOS and differential LVDS PCB interconnect testability. These features help to reduce test time, reduced testing and development costs. 3.3V power supply circuit, CMOS process, and LVDS I / O, to ensure that the entire industrial temperature range (-40 ? to +85 ?) to achieve high performance and low power consumption.
SCAN90CP02 can actually eliminate jitter to improve system reliability, lower cost so that the user can use the line to achieve interconnection. As SCAN90CP02 with pre-emphasis feature, so not only can perform normal switching function, and can be used as a buffer to the existing FPGA, ASIC and serial / deserializer (SerDes), etc. LVDS signal amplification. In addition, the LVDS output of the circuit does not support multi-drop (multidrop) BLVDS environment.
SCAN90CP02 the following features:
the transmission rate per channel up to 1.5Gb / s.
Low power consumption, dual repeater mode, the highest rate when the current is only 70mA.
low output jitter.
configurable pre-emphasis function (0/25/50/100%) can be driven lossy backplanes and cables.
has through (Flow-through) pin lead.
LVDS / BLVDS / CML / LVPECL input, LVDS output.
for IEEE 1149.1 and 1149.6 standards.
3.3V single power supply.
Input and output can be individually controlled to reduce power consumption.
industrial temperature range (-40 ? to ± 85 ?).
SCAN90CP02 28-pin LLP package or 32-pin LQFP package.
Pre-emphasis circuit to compensate for loss of long-distance transmission or a transmission medium. To minimize power consumption, the circuit for each output provides a separate pin. And pre-programmable device by function.
2 SCAN90CP02 application
In my design projects, the need to use up to 600Mb / s data rate to transfer from the transmitter and receiver for data transceivers, modulation and channel matching tasks. In order to test the quality of the data communication system is good or bad, I also designed a high-speed bit error rate tester. The tester by the three circuit boards, namely the clock generation board, hair board and received board. In the clock generation board and the board with a piece of hair SCAN90CP02, one can make the output signal of the circuit board connector as close as possible to reduce the core of the circuit board wiring pressure to position the more free; second is the completion of power level translation task, the level will be converted into LVDS LVPECL levels; third is to compensate the loss of alignment, to ensure better signal transmission quality. The BERT block diagram shown in Figure 2, the figure highlights SCAN90CP02 the connection. The following details of the test instrument in a variety of circuit boards.

(1) bell plate. Clock board SCAN90CP02 configured 1:2 splitter mode, EN0, EN1, SEL0 and SEL1 are set to low. Clock Plate in 300MHz LVPECL clock signal level, the SCAN90CP02 converted into 2-way LVDS level, BERT hair were sent to board and received board.
(2), made board. Development board with Xilinx's VirtexII series XC2V250 circuits as the core, by a number of peripheral circuits and control circuit to complete the pseudo-code generation, data framing, and the string conversion functions. Output of 600Mb / s data and 300MHz clock by SCAN90CP02 break through the connector to the transmitter. SCAN90CP02 dual-channel configuration interrupt control mode, SEL1 is set high, the other side set the level control.
(3) collection plate. Xilinx's board to receive VirtexII series XC2V250 circuits as the core, by a number of peripheral circuits and control circuit. To achieve frame synchronization, data recovery, serial and change, more counts and error statistics display.
SCAN90CP02 the pre-emphasis control side DIP switch used to select high and low, in order to increase design flexibility.
3 Conclusion
In many applications, especially with backplanes and high-loss cable, some circuits (ASIC and FPGA, etc.) of the drive capacity is often inadequate, which requires the use of the circuit with a pre-enhancements (such as SCAN90CP02) prior to signal amplification, the receiver will not only ensure adequate input signal voltage, but also increase the transmission distance and improve the signal quality. Especially the use of LVDS transmission, its greatly enhanced anti-jamming capability, but also reduces the electromagnetic radiation