Abstract:This article describes TI 's serial A / D converter TLC1540/1541 structure , characteristics and working principles , discusses the chip with the MCU to connect the software and hardware interface design . Keywords :MCU Interface Serial ADC Abstract:The structure, features and principle of serial A / D converter TLC1540/1541 are introduced in this paper, the software and hardware design of its interface with MCU are also dicussed in detail. Keywords:Serial ADC Monolithic Microcomputer Interface In digital measuring instruments and industrial measurement and control systems, first of all need to be measured with sensors such as temperature , humidity, pressure, flow , level and other parameters into electricity , through the enlarged handle evacuation A / D??devices into digital content , and then Further operations , storage , display and print processing . Traditional A / D converter digital output commonly used in parallel , to take up system resources more bus . TI Introduces 10-bit A / D converter TLC1540 and TLC1541 serial data line used to facilitate the interface with the microprocessor , the bus resources conservation . The following detailed description of its structure, properties and and MCU interface design . 1. TLC1540/1541 features 1.1 Overview TLC1540/1541 is a 10-bit switched capacitor successive approximation A / D converter based on the structure of the CMOS A / D converter. They are designed through the three-state output and analog input and the microprocessor or peripheral serial interface , you can also work independently. TLC1540/1541 only input / output clock (I / O CLOCK) and chip select input for data control , the highest I / O CLOCK input frequency of 1.1MHz, applications and TLC540/541 similar . The difference is that TLC1540/1541 provides on-chip system clock , often working without the need for an external clock at 2.1MHz . On-chip system clock allows internal device operation is independent of the serial input / output timing and allow TLC1540/1541 as many software and hardware work as required . I / O CLOCK and the internal system clock can be achieved with high-speed data transfer and 32 258 conversions per second conversion rate . TLC1540/1541 with common control logic and automatically under the control of work or work in the MCU chip sample - hold circuit , there are differential high-impedance reference voltage inputs , easy to implement conversion ratio (ratiometric conversion) high-speed converters , calibration ( scaling) as well as logic circuits and power supply noise isolation . The switched-capacitor successive approximation converter circuit design allows the time in less than 21µs maximum error is 0.5 least significant bit (TLC1540) and +1 least significant bit (TLC1541) to achieve conversion accuracy . TLC1540C/1541C operating temperature range is 0 ? -70 ?, packages are SO, PCC and PDIP three forms . 1.2 Features TLC1540/1541 has the following characteristics: 10-bit resolution A / D converter Microprocessor Peripheral or independent work Differential reference input voltage Conversion time 21µs Max 12 -channel analog switches Software controlled sample chip - to keep Total unadjusted error (Total Unadjusted Error): TLC1540: +0.5 LSB Max TLC1541: +1 LSB Max 2.1MHz typical internal system clock Wide supply voltage range of 3V-6V Low-power 6mW Max Can be ideal for battery-powered portable devices , including low-cost , high performance applications Pins and control signals with the TLC540, TLC545 8?A / D converter and TLC548/549 8?A / D converter compatible CMOS technology 1.3 Functional Block Diagram and Pinout TLC1540/1541 functional block diagram shown in Figure 1 , mainly by the sample - hold circuit , multi- channel analog switch , on-chip clock circuits , switched capacitor A / D converter circuit , data output registers , control logic and data selection and drive and some other Composition . Small and the pin PDIP package TLC1540/1541 arrangement shown in Figure 2 . Pin diagram of Figure 2 TLC1540/1541 2 Features and working principle 2.1 TLC1540/1541 limit the scope of work within the parameters Power supply voltage VCC 6.5V Input voltage range of any input -0.3V ~ VCC +0.3 V Output voltage range -0.3V ~ VCC +0.3 V Peak input current range of +10 mA Peak total input current range of +30 mA Operating temperature range ( natural ventilation) TLC1540C/1541C 0 ? ~ 70 ? Storage temperature range -65 ? ~ 150 ? Lead Temperature ( from the shell 1.6mm) 260 ? 10? 2.2 Work TLC1540/1541 is the perfect single chip data acquisition system . Each device includes an internal system clock , sample and hold, 10-bit A / D converter, on-chip registers and control logic . To increase flexibility and access speed , the device has two control inputs : I / O CLOCK and chip select . These control inputs and TTL- compatible 3- state output is easy with a microprocessor or micro- computer serial communication . Device can 21µS or less to complete conversion . TLC1540/1541 31µS repeat each complete input - transformation - output cycle . Within the system clock and I / O CLOCK independent use and do not require any special speed or phase relationship between them . This independence simplifies the hardware devices and software control tasks . Because of this independence and the internal system clock generation, control only concerned about the use of hardware and software I / O clock read out the results of the previous converter and start conversion . Within the system this way drives the clock converter circuit to control the hardware and software do not involve this task. Timing of their work shown in Figure 3 . When is high , DATA OUT is in high impedance state and the I / O clock (I / O CLOCK) is prohibited . When using another TLC1540/1541 device, such a chip select control function allows I / O CLOCK terminal and its counter parts share the same control point . When using multiple TLC1540/1541 devices , this is also used to make the necessary control logic side of at least . Control sequence has been designed to start the conversion and the time required to achieve conversion results and work at least . The normal control sequence is: (1 ) pulled to low . In order to end the noise generated by the smallest error in the identification of a low jump before the internal circuits within the system clock ? to wait after the rising edge of the subsequent falling edge of the two . When the device when used in noisy environments , this technology can be used to protect them from the noise of the device . When becomes low, the previous conversion result of the most significant bit (MSB) began to appear in the DATA OUT terminal . Figure 3 TLC1540/1541 the work of the timing diagram (2 ) The former four I / O CLOCK cycle, the rising edge of the input channels are logical addresses, address of the previous high . In this four pulse output of the falling edge of the previous conversion results , respectively the second , third, fourth and fifth most significant bit . In the fourth high to low transition , the on-chip sample and hold circuit to begin addressing the simulation of analog input channels sampled . Sampling operation is mainly the internal capacitors to the analog input voltage charge level . (3 ) then the five I / O CLOCK cycle, added to the I / O CLOCK terminal , in which the falling edge of clock cycles , 6 , 7 , 8, 9, 10 conversion bits are shifted out . (4 ) the last ( No. 10 ) clock cycles are added to the I / O CLOCK. This clock cycle high to low transition to on-chip sample and hold circuit started to keep functional . 44 system clock cycles following completion of conversion . At 10 I / O CLOCK cycle , you must become a high , or I / O CLOCK must remain low up to at least 44 system clock cycles for completion of the maintenance and conversion . Conversion cycle in a number of chip select signal may remain low . In a number of conversion cycles to maintain a low chip select signal must pay special attention to prevent I / O CLOCK line flicker noise . In the event of a flicker, then the microprocessor / controller and the device between the I / O timing will be out of sync . In addition , if the chip select signal becomes high , it must remain high until the conversion ends. Otherwise, the chip select signals valid high to low hop side will cause the reset Ershi ongoing conversion failed. In the 44 system clock cycles before the occurrence , by completing steps 1 through 4 could start a new conversion , while the ongoing conversion of suspension . This action produces results , rather than the previous conversion result of the ongoing transformation . For some applications , such as strobe (strobing) applications, need to start at a specific time point conversion . This device is able to adapt these applications . Although the on-chip sample and hold in the first four effective I / O clock cycle began sampling along the negative , but valid until the 10 I / O clock cycle before the negative edge to maintain function do not start . TLC1540/1541 continue sampling the analog input until the I / O clock falling edge until the 8th . Control circuitry or software then immediately lower the I / O CLOCK and starts to maintain function and the time required to maintain analog signal and the conversion starts . 3 TLC1540/1541 with MCU Interface Design As TLC1540/1541 way to transfer serial data, and the SCM connection will only take four port lines . One I / O CLOCK, ADDRESS IN and DATA OUT can be another TLC1540/1541 or external unit share . Specific interface method shown in Figure 4 , the figure then chip select terminal P10 , P11 then the clock end , P12 access the data output , P13 then address input. Conversion results can be read by P11 MCU in the analog clock signal . Procedures are as follows : MOV R0, # 40H; results of the first address buffer MOV R1, # 0; selected channel CLR P11 CLR P10 CLR A LOOP: LCALL READ; time high eight previous results DJNZ R7, LOOP MOV R0, A INC R0 MOV R7, # 2 CLR A LOP1: LCALL READ; read the previous results of low- two DJNZ R7, LOP1 MOV R0, A SETB P10 INC R0 LCALL DELAY; 50 µs delay subroutine CLR P10 MOV R7, # 8 CLR A LOP2: LCALL READ; Reading time results DJNZ R7, LOP2 MOV R0, A MOV R7, # 2 CLR A LOP3: LCALL READ DJNZ R7, LOP3 MOV R0, A SETB P10 ? ? READ: PUSH A MOV A, R1 RLC A MOV R1, A POP A MOV P13, C SETB P11 CLR P11 MOV C, P12 RLC A SETB P11 RET DELAY: ? ?; delay subroutine slightly References 1 Texas Instruments.TLC1540/1541 Application Guide Ref.Vol3, Texas Instruments Inc., 1999 2 He Limin . MCS-51 family of SCM application system design. Beijing University of Aeronautics and Astronautics Press, 1995