Abstract: This paper presents a method of using video A / D chip TLC5510 and low-grade DSP chip TMS320F206 achieve image acquisition interface design, interface program also given for the low-end DSP chip, the application provides a new way.
DSP is digital signal processing theory and super-large scale integrated circuit VLSI technology, integration of the crystallization. DSP technology is now widely used in communications, voice, image, aerospace, instrumentation and other areas of information processing in the promotion of contemporary digital is playing an increasingly important role.
In the use of telephone lines transmit video images of this area of low bit-rate multimedia communication, if you use a dedicated image processing chips, such as the SAA7110, 8 × 8 3104VCP, as well as the company's dedicated LSI chips, or use a high-speed computing performance of high-grade DSP for image processing, will cause the price marked up substantially. This article describes the adoption of TI's low-end DSP chip TMS320F206 and video A / D chip TLC5510 the image acquisition card, for the low bit-rate multimedia communication provides an inexpensive solution.
TLC5510 chip and chip TMS320F206
About TLC5510
TLC5510 is a CMOS, 8 Wei, 20MSPS A / D word converter ADC, which uses a half-flash semiflash architerture structure. TLC5510 single 5V power supply and consumes only 100mW of power. It also has an internal sample and hold circuits, high impedance of the parallel output, and internal reference resistors.
And compared to flash converter flash converter, half-flash architecture reduces power consumption and chip size. Two-step process through the 2-step-process to achieve conversion, can significantly reduce the number of comparators. Conversion data latency of 2.5 clock cycles.
No external reference voltage source and precision resistors, only using the internal reference resistance and VDDA can be achieved in full-scale conversion range of 2V. 25 ℃, the linearity error of ± 0.75LSB, in the whole temperature range is the maximum linearity error of ± 1LSB. 25 ℃ when the differential linearity error of ± 0.5LSB, in the whole temperature range is the maximum differential linearity error of ± 0.75LSB.
About TMS320F206
TMS320F206 is TI has introduced a DSP chip, which is based on high-speed fixed-point TMS320C5x digital processing chip, the Harvard architecture in parallel with improved separation of program and data bus, high-performance CPU and efficient instruction set and so on. Its main features are as follows:
CPU has a 32-bit CALU, 32-bit accumulator, 16 × 16-bit parallel multiplier, three shift registers, eight 16-bit auxiliary registers.
Memory with 224K words addressable memory space, 544 words on-chip DRAM, 4K words on-chip SRAM, or 32K words on-chip flash memory.
Command speed 50ns, 35ns and 25ns single instruction cycle.
A software programmable timer peripheral circuits, software-programmable wait state generator, on-chip PLL clock generator, synchronous and asynchronous serial series.
Hardware interface circuit design
TLC5510 front-end circuit design
TLC5510 front-end circuit shown in Figure 1.
In the circuit, analog and digital power supplies VDDA power VDDD independent of each other. VDDA and digital ground and between AGND to DGND and simulation VDDD with 4.7μF capacitor between all, 0.1μF capacitors and iron oxide magnetic ring and the elimination of power supply decoupling ripple. AGND and DGND be split to avoid the digital signal to an analog signal to bring the noise. Amplified video signal directly added to the TLC5510's 19 feet. TLC5510 the clock signal is generated by TMS320F206 clock signal output pin CLKOIU1 provide.
TLC5510 and TMS320F206 Interface Circuit Design
TLC5510 and TMS320F206 interface circuit shown in Figure 2
TLC5510 figures connected with the TMS320F206 ground. TLC5510 data output due to an internal buffer, so TLC5510 feet D1: D8 and TMS320F206 feet D0: D7 directly connected. TMS320F206 feet of CLKOUTI through a small resistance to the TLC5510 to provide the clock signal. TMS320F206 pin A11 and for the logic control, when the A11 is logic high, logic low, TMS320F206 can read the sampled data from the TLC5510.
TMS320F206 serial communication with the computer
Into TMS320F206 image data through serial port to 9600 b / s rate into the computer, the computer to store data in cache, and then the conversion process with the image pixel on the monitor display.
Interface Programming
The procedures for the initialization of constants
(1) sample-based data storage area starting address of 0900h
(2) The number of samples set 1000h
(3) Let A / D address 0800h
The procedural steps
An initialization TMS320F206
2 Load the appropriate ARn
3 strobe TLC5510
4 reads A / D conversion value
5 Initialize UART
6 to the number of UART transmission
7 end of the process
The specific procedures
. title "TLC5510 Interface"
. copy "init.h"
. copy "vector.h"
. text
ADC_Addr. Set 0800h; set the address of TLC5510
Mem_pointer. Set 0900h; set the sampling data storage area
Start Address
Count. Set 1000h; set the number of sampling
start: lar ar2, # ADC_Addr
lar ar3, # Mem_pointer
lar ar4, # Count
- Start A / D conversion
ldp # 6h; Settings page pointer to point to the
50h × 6 = 0300h at
splk # Count, 0h; put the number of samples into the 0300h
Iar ar4, # 0300h; to AR4 points to 0300h
mar , ar4; to AR $ set to the current register
rpt , ar3; set RPTC register, put the
AR3 set to the current register
in +, ADC_Addr, ar4; read and store the A / D conversion
Results
transmit data to the computer through the UART
initialize UART port
clrc CNF; to B0 block map data space
ldp # 0h; set the pointer to point to leaf 0h Service
setc INTM; ban on all interrupts
splk # 0ffffh, ifr; clear interrupt
splk # 0000h, 60h
out 60h, wsgr; set zero wait
splk # 0c180h, 61h; the UART port reset
out 61h, aspcr; allow the I / O interrupts
splk # 0e180h, 61h
out 61h, aspcr; open the I / O Fracture
splk # 4fffh, 62h
out 62h, iosr; to prohibit automatic baud rate
splk # 00082h, 63h
out 63h, brd; set the baud rate to 9600
splk # 20h, imr; allow UART interrupt
lar ar3, # 0900h; recovery AR3
lar ar4, # Count-1; restore AR4
mar , ar3; set to the current register AR3
clrc intm; Open interrupt
uart1: setc xf; to xf set a start mass number
mar , ar3; to the current register set AR3
out +, adtr; outgoing data, the AR3 plus 1
wait: clrc xf; close xf, to stop mass number of
mar ar2; to the current register set AR3
in, 0fff6h; read the status register IOSR
bit , 4; detection section 12 whether 0
bcnd cont, tc; If 0 wait until IOSR
The first 12 to 1
b wait
skip: splk # 0020h, ifr; clear interrupt
clrc intm
mar ar4; transmission minus a number of
banz uart1, ar3; not pass end, then jump to UART1, pass down a number of
ret; Back
inpt1: ret
inpt23: ret
timer: ret
uart: ret
codtx: ret
codrx: ret
. end
We will interface TMS320F206 with the TLC5510 is designed for remote multimedia coal mine low bit rate communication monitoring system, the initial progress has been made, this application can be TMS320F206 for image processing to provide a line of thought, thus opening up a low bit-rate multimedia communication an inexpensive way.
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