Abstract: A DSP-based high-speed USB2.0 interface and data acquisition and processing system works, design and implementation. The high-speed data acquisition and processing system using TI's TMS320C6000 digital signal processor and USB2.0 interface chip Cypress companies can realize high-speed acquisition and real-time processing, with a wide range of applications.
As the digital signal processing theory and the continuous development of the computer, the modern industrial production and scientific and technological research needs the help of digital processing methods. Digital processing is a prerequisite for the digitization of the object of study, data acquisition and processing technology is increasingly taken seriously. In image processing, transient signal detection, software radio and some other areas are demanding more high-speed, high accuracy, high real-time data acquisition and processing technology. Now high-speed data acquisition and processing card commonly used high-performance digital signal processor (DSP) and high-speed bus technology framework. Complete the computation for large DSP real-time processing algorithms, high-speed bus technology is finished processing the results of the rapid transmission of data or samples. TI or ADI DSP mainly the company's products, high-speed bus can use ISA, PCI, USB and other bus technologies. At present, the more extensive the PCI bus, although it has many advantages, but there are serious shortcomings; vulnerable to the environmental impact of the chassis, the number of slots by the computer address, interrupt resource constraints, many devices can not be articulated . With its easy installation USB bus, with the high, easy to expand, etc., which have a standard USB2.0 transfer rate up to 4800bps, has gradually become the mainstream of computer interface. This article describes a USB2.0 interface and high-performance DSP with high-speed data acquisition and processing system, mainly for the fiber communication wavelength DWDM system designed for testing and adjustment can also be used as image processing, radar signal treatment and other related fields.
1 high-speed data acquisition and processing systems and devices use the principle
The high-speed data acquisition and processing system hardware components are: high-speed ADC, high speed and large capacity data buffer, high-performance DSP and USB2.0 interfaces. System block diagram shown in Figure 1.
High-performance DSP with TI's TMS320C6000 fixed-point DSP family in the TMS320C6203B; high-speed ADC using TI's ADS5422, 14-bit sample, the maximum sampling frequency is 62MHz; PC computer interface with USB2.0, theoretical maximum data transfer rate of 480Mbps, the device Companies selected Cypress EZ-USB FX2 series CY7C68013; data buffer using IDT's high-speed large-capacity FIFO devices IDT72V2113; program stored in Flash memory, the device used SST291E010. The following describes each of the main features of each device.
(1) TMS320C6203B
TMS320C6203B TI's high performance in the United States TMS320C6000 digital signal processor of a series, using the modified Harvard bus architecture, a total of 1 set of 256-bit program bus, two 32-bit program bus and a set of dedicated 32-bit DMA bus; 8 function internal units can operate in parallel, a maximum operating frequency of 300MHz, the maximum processing capacity 2400MIPS; the internal integration of the peripheral device interface, such as external memory interface (EMIF), the external expansion bus (XB), multi-channel buffered serial port (McBSPs ) and the host interface (HPI), and external memory, co-processor, the host and serial device connection is very convenient.
(2) ADS5422
TI ADS5422 is produced by the U.S. high-speed parallel 14-bit ADC, the maximum sampling frequency of 62MHz, the sampling frequency is 100MHz,, SNR is 72dB, SFDR is 85dB. Analog input can be single-ended input or differential input mode, the maximum input signal peak value of 4V, single 5V power supply. Fully compatible with 3.3V digital signal output device, and provides full-scale input signal and output digital signal flags valid flags, and other devices so as to facilitate the connection.
(3) IDT72V2113
IDT72V2113 IDT produced by the U.S. high-speed large-capacity FIFO memory device (FIFO). The maximum operating frequency is 133MHz; capacity of 512KB, you can easily pin the capacity set to 512K × 9bit or 256K × 18bit two ways; IDT72V2113 can set the standard operating mode or FWFT (First Word Fall Through) mode, and provide full, half full, completely empty, the full and waited in vain for five signs will signal; very convenient for capacity expansion. Capacity expansion is a major feature of IDT72V2113 extended word length can be divided into deep extension and expansion of the word. Can be easily extended through the multi-chip IDT72V2113 form larger capacity buffer, and the electrical connections simple and reliable.
(4) CY7C68013
Cypress CY7C68013 in the United States launched a USB2.0 chip is a fully integrated solution that takes up less board space, and reduce development time. CY7C68013 main structure is as follows: including an 8051 processor, an intelligent serial interface engine (SIE), 1 ? USB transceiver, 16KB on-chip RAM (including 4KB FIFO) memory in the main a General Programmable Interface (GPIF) .
Figure 3
CY7C68013 unique architecture has the following characteristics:
includes an intelligent serial interface engine (SIE), it performs all basic USB functions, freeing the embedded MCU to be used to implement other rich features to ensure continued and effective high-speed data transmission;
large capacity with 4KB FIFO for data buffering, when as a slave device, can be Synchronous / Asynchronous FIFO interface with the main equipment (such as ASIC, DSP, etc.) connection; as the main device, through general programmable interface ( GPIF) any form of control waveforms to achieve with other slave devices connected to easily compatible with most bus standards, including ATA, UTOPIA, EPP and PCMCIA, etc.;
firmware, software configuration, will need to run in the CY7C68013 firmware, stored in the host, when the USB device connected to the host, download to the device, so that no changes to achieve in the case of the hardware is easy to change the firmware;
to the full realization of USB2.0 (2000 Edition) protocol, backward compatible with USB1.1.
2 high-speed data acquisition and processing system of the hardware connection
2.1 analog signal input circuit
ADS5422 analog inputs can be taken single-ended input or differential input mode. Connected single-ended input is relatively simple, but the anti-noise performance is poor, so we adopt differential input in order to minimize signal noise and electromagnetic interference, especially in differential input mode can even harmonics through the pros and cons of all anti-input signal is essentially cancel each other.
ADS5422 differential input analog signals need to use both IN and IN pins, the hardware connection method shown in Figure 2. The figure, the first to use the amplifier OPA687 and a single-ended RF signals into differential signals, and then input to the ADS5422, ADS5422 which the common CM and RF transformer common connection, RF transformer turns ratio should be determined according to the signal. To enhance the stability of the signal in the ADS5422 be added before each signal input RC low-pass filter circuit, Figure 2, as recommended by Rt 50O, Rin is 22O, Cin is 10pF, these components can be adjusted depending on the signal, Under normal circumstances in the 10 ~ 100O resistance value between the capacitance between the 10 ~ 200pF.
Figure 4
2.2 ADS5422 connection with the IDT72V2113
Although the ADS5422's power supply voltage of 5V, but the output of the digital signal level compatible with 3.3V level, so no level converter chip, as long as the ADS5422 data lines and data lines connected to IDT72V2113. However, ADS5422 sampling and storage of sample data to IDT72V3113, the two operations are very strict on the timing configuration requirements, and if the timing relationship between the two was not very good match, an error occurs, or out of the number of data storage. How simple, reliable sampling and storage is designed to achieve this part of the circuit difficult. General approach is that by programmable logic device (CPLD or FPGA) to achieve between the ADC and the FIFO memory timing, that is, by the CPLD or FPGA to control the ADC sampling and FIFO memory write operation. However, by carefully review the work of the ADS5422 and IDT72V2113 timing diagram, found a simple and reliable implementations, this method does not require CPLD or FPGA can be achieved with the timing between the two.
First, the work of ADS5422 timing diagram shown in Figure 3, where t1 is the sampling clock edge to output data is invalid jump time between, namely, data hold time, the size of 3ns. View IDT72V2113 the documentation we can see that its write operation, data lines can be kept longer than 1ns meet the requirements. Therefore, ADS5422 and the timing between IDT72V2113 can be used with the following simple implementation: ADS5422 sampling clock and write clock IDT72V2113 use the same clock source, so that each hop along on the clock, ADS5422 analog to digital conversion, while the last sampling clock output data to DT72V2113 inside.
2.3 C6203B connection with the IDT72V2113
C6203B and C6203B IDT72V2113 connection is through an external expansion bus (XB). C6203B external expansion bus (XB) a width of 32 bits, you can achieve seamless connectivity and synchronization FIFO, you can also seamlessly interface to the four FIFO write or implement three FIFO write port and a FIFO read interface. Achieved through the seamless interface to FIFO read, FIFO must be connected to XCE3, the data sent by DMA to the C6203B way from IDT72V2113 chip RAM, the specific connection shown in Figure 4. Figure 4, the four IDT72V2113 through the expansion of word length and word formation of deep-2MB of data input buffer, the input data bus (D0 ~ D15), the output data bus (Q0 ~ Q15), read enable (REN), read clock (RCLK ), write enable (WEN), write clock (WCLK) signal, and the empty flag (PAE) is a four IDT72V2113 the formation of the corresponding signal combinations; XCE3 for external expansion bus (XB) space select signal, XFCLK for external expansion bus (XB) of the output clock, EXT_INT4 is C6203B external interrupt 4, DX0 used as a general-purpose output port, control IDT72V2113 write enable signal.
2.4 CY7C68013 connection with the C6203B
CY7C68013 USB2.0 is a very easy implementation program, which provides connections with the DSP or MCU interface, the connection in two ways: Slave FIFOs and Master programmable interface GPIF. In this scenario, the selected Slave FIFOs way, asynchronous read and write. Slave FIFOs way to the slave mode, DSP can be the same as the FIFO read and write ordinary multi-storey house on the CY7C68013 to read and write buffer FIFO. Specific circuit connection shown in Figure 5. FLAGA, FLAGB and FLAGC is the internal FIFO status flag CY7C68013, C6203B through a common I / O port to get the FIFO empty, half full (half-filled by the user to set the threshold), and full of such status information. C6203B CY7C68013 internal FIFO of choice and submit the packet is through common I / O port to achieve. C6203B EMIF interface through CY7C68013 CE2 space to read and write operations. Working process: DSP to send data via USB to the PC, the first view empty, half full and full three state signal, and then write the appropriate size to the USB data to ensure data does not overflow; PC via USB to the DSP unit Send command word, USB DSP via an interrupt to notify the command to read the word.
3 USB Software
USB interface, there is considerable development work is about the development of USB software, USB software includes work in three areas: the firmware (firmware) design, driver design and the design of the host-side applications.
3.1 firmware design
CY7C68013 firmware is running on the program, can be assembly language or C language design, its main function is to control the CY7C68013 USB driver to receive and process the request (such as device descriptor request, request, or set the device status, request, or set the device interface USB2.0 standard requests, etc.), control CY7C68013 control instruction receiving applications, store data and real-time through CY7C68013 uploaded to PC and so on.
The program in firmware design ideas are as follows:
the CY7C68013 operates asynchronously from the FIFO (Asynchronous Slave FIFO) mode. The corresponding register operations as: IFCONFIG = 0xCB.
CY7C68013 work with a variety of ways, in addition to any control as to produce the master-chip waveform, even as a slave device can also choose asynchronous or synchronous mode. The relationship between the DSP, the program selected from an asynchronous way.
to 4KB of the FIFO corresponding to the two endpoints (EndPoint), which EndPoint2 and EndPoint6. The corresponding register operations as: EP2CFG = 0xA0, EP6CFG = 0xF2.
EndPoint2 and EndPoint6 the contents in the corresponding 2KB FIFO (hereinafter respectively referred to as FIFO2, FIFO6), USB to upload and store the data received. One EndPoint2 is OUT type, is responsible for receiving data from the host; EndPoint6 as IN type, is responsible for sending data to the host. In addition, EndPoint2 EndPoint6 are used with the bulk (BULK) transmission, this approach defined relative to the other USB2.0 transmission with reliable data transfer rate higher characteristic, is the most common means of transmission.
on the FIFO configuration. The corresponding register operations as: EP2FIFOCFG = 0x11, EP6FIFOCFG = 0x0D.
The program will FIFO2, FIFO6 set to automatic mode. Here the so-called "automatic" refers to the data transmission process, the kernel does not need CY7C68013 in 8051. If special needs can be set manually, so that 8051 can modify the data shown in Figure 6. There will also be configured as a 16-bit FIFO interface.
other operations. Weile improve the USB transfer function and enhance the robustness of the firmware must also be accompanied by other design, which includes the automatic empty FIFO reset, individual orders and other functions, in this not discussed in detail.
3.2 Driver
USB system driver layered structure model, were higher in the USB device drivers and low-level USB Function layer. USB Function layer which consists of two parts: a more advanced module universal serial bus driver (USBD) and lower-level host controller driver module (HCD). Stratification in the USB module, USB Function layer (USBD and HCD) provided by the Windows to manage USB device drivers and USB communication between the controller; Loading and Unloading USB driver; and universal USB device endpoint (EndPoint ) to establish communications and perform device configuration, data and USB protocol framework and package format, two-way conversion tasks. Currently offers a variety of Windows USB device driver, but not for real-time data acquisition equipment, the USB device driver to be written by the developers themselves.
USB device driver development, the company's development kit can be used Numega Driver Works and Microsoft Corporation 2000DDK, and to VC + +6.0 as a supplementary development environment. Driver Works provides wizard-driven, according to the needs of users, automatic code generation framework, reducing the difficulty of development and shorten the development cycle. However, Cypress USB development company for the convenience of the user interface, the CY7C68013 development package provides a generic driver, the program without modification, the DDK compiled directly. In this design, the use is the generic driver.
3.3 Application Design
Implement the host application is the main board from the high-speed data acquisition and processing of data after the taking, storage, display processing structure and data acquisition processing board to send control commands. In Windows 2000, we use application development tool is VC + +6.0.
4 System Works
After power, ADS5422 has been working, whether the sampling data generated in the store IDT72V2113 by C6203B the DX0 pin state to decide. C6203B initialization, the external expansion bus synchronous FIFO XCE3 set to read mode. DMA channel 0 configuration for each of the transmission 1, 1024 half-words each frame, synchronization event is set to external interrupt 4 polarity is high, initialize timer 0, timer interval of 22ms. When an external sync signal comes in, start the timer 0, and manually start the DMA channel 0, and set DX0 low. ADS5422 sampling data generated start writing IDT72V2113, when the timer 0 interrupt arrives, set DX0 is high, the write off IDT72V2113 enabled, the sampling data is no longer stored within IDT72V2113. As data is written to IDT72V2113, when its internal data is greater than 1023 half-word, IDT72V2113 of the empty flag signal (PAE) from low to high, making the C6203B external interrupt valid, and thus trigger the DMA transfers, C6203B the DMA channel 0 external expansion bus (XB) 1024 half-word read data stored in internal RAM, send a transmission after the interruption to the C6203B, C6203B notification process the data. C6203B processed data, through the USB2.0 interface to send the results, and then restart the DMA channel 0, the next DMA transfer. This cycle until all the data. The arrival of the moment when an external sync signal, the next round of data collection process.
5 Conclusion
This paper describes the DSP-based high-speed USB2.0 interface and data acquisition and processing system, system configuration, hardware, connectivity, and USB2.0 drivers and firmware development. The practical verification, the system is reliable, is a good high-speed data acquisition and processing solutions.