Abstract: USB-based high-speed data acquisition card design and implementation. Detailed account of the data acquisition card hardware design, and briefed the firmware, drivers and application software design.
Introduction
Data collection and scientific research in modern industrial production the important position in the increasingly prominent, and real-time requirements of high speed data acquisition is also rising. Signal measurement, image processing, audio signal processing and some other high-speed, high precision measurement, high-speed data acquisition needs. Now a common high-speed data acquisition card is a PCI card or the general multi-ISA cards, there are many shortcomings of these capture cards, such as the installation trouble, the price is expensive, especially by the slot machine number, address, interrupt resource constraints, poor scalability.
Universal Serial Bus USB is used to connect peripheral devices with the new standard interface between the computer bus. It is a fast, bidirectional, synchronous transmission, cheap and can hot plug serial interface. USB technology is to achieve the integration of computer and communications made for the expansion of an industry standard PC architecture. USB-based high-speed data acquisition card, full use of the advantages of USB bus, it will be more and more accepted by users.
Principle 1 USB data acquisition card
1.1 USB Overview
Universal Serial Bus USB is an abbreviation in English, Chinese meaning is "Universal Serial Bus." It supports plug and play in the host and the various data transfer between peripherals. It is intended to transfer data from the host of standard protocols, various devices on the bus share the USB bus bandwidth. When the bus peripherals and the host at runtime, allowing freedom to add, install and use and removal of one or more peripherals. USB bus technology proposed is to use a single bus, to meet the needs of a variety of applications. USB1.1 protocol supports two transmission speed, that is, high-speed low-speed 1.5Mbps and 12Mbps. In order to compete in the high-speed interface of a place, in 2000 released a USB2.0 protocol backwards compatible with USB1.1 protocol, the maximum data transfer rate up to 480Mbps, which makes USB printers and other needs of rapid transmission of large capacity peripheral data more attractive.
USB data acquisition in order to meet the actual needs of higher transmission speed, selected Cypress's built-in USB interface to micro-controller chip EZUSB FX2 series, developed with a USB interface, high speed data acquisition card.
1.2 System Block Diagram
USB system is a master-slave system, rather than on the other (peer-to-peer) systems. In the master-slave system, the command is issued by the master, but can only receive commands from the device, only the master device to read data from the device to submit data. Shown in Figure 1, the USB controller and the peripheral circuits need a FIFO, to act as a data buffer. Then, in the USB device from the device sends data to the master that there is a problem: FIFO how to meet the requirements. In order to meet high-speed data acquisition in the application of real-time streaming data scale, to avoid FIFO overflow, in our system, through the FPGA and SDRAM capacity to construct a FIFO (as shown in Figure 1, dotted), can provide a low cost and can meet the high-speed real-time streaming data transmission solutions.
Figure 2 Click to enlarge
2 USB data acquisition hardware
2.1 EZ-USB FX2 (CY7C68013) chip
Cypress's EZ-USB FX2 Series USB2.0 protocol chip is the first line with one of the microcontroller, which integrates a USB2.0 protocol transceivers meet (transceiver), a serial interface engine (SIE), enhanced 8051 core and the programmable peripheral interface. FX2 series chip's unique structure makes data transfer speeds up to 56Mbps, the maximum bandwidth to meet the USB2.0.
EZ-USB FX2 microprocessor is an enhanced 8051 core, the performance up to the standard 5 to 10 times 8051, and with the standard 8051 instruction compatible. Enhanced 8051 core with RAM SAI Guo memory for program instructions and data, making EZ-USB FX2 has a "soft" characteristics, that is, you can write your own program instructions to implement the required functionality. EZ-USB FZ2 using enhanced SIE / USB interface (called the USB core), the Ministry itself, through the implementation of USB protocol to simplify the work of the 8051 coding. This USB Leng complete with hardware, simplifying the preparation of the firmware code. Firmware code for the use of the host through software downloaded ways. Take full advantage of this approach within FZ2 8KB RAM to load the 8051 code and data. Because EZ-USB FZ2 has the ability to re-enumeration, enumeration is initialized so, the user does not need off days can load the new device descriptor. Device descriptor and the 8051 code can be accessed through the host in the disk file to download, only manufacturing firms, product number and unit number from the start from a 16-byte EEPROM download in hardware. In this way, you can easily upgrade the software from the host USB bus device and modify the firmware code.
EZ-USB FX2 GPIF Yiji General Programmable Interface Master / Slave Duandian corresponding FIFO 8 / 16 bit data bus, can be easily achieved some mainstream FX2 and the current through the interface (such as ATA, UTOPIA, EPP, PCMCIA, and most of the DSP processor) of interconnection. It comprises seven endpoints, endpoint 0 and endpoint 1 IN and OUT, there are endpoint 2,4,6 and 8. Among them, the first 3 the size of the endpoint is fixed 64 bytes, after the endpoints default size is 4 512 bytes of Level 2 FIFO, endpoint 2 and 4, the default is OUT endpoint endpoint endpoint endpoint 6 and 8, the default is IN endpoint 2 and 6, respectively, while the endpoints can be defined as two, three or four of the memory, the size of each level can also be 512 bytes or 1024 bytes. EZ-USB FX2 direction from the point of view, an end is equivalent to send and receive data through the bus buffer, EZ-USB FX2 is read from the OUT endpoint buffer data transfer through USB IN endpoint buffer data is written. It is demanding perfection speed (12 Mbps) and high-speed (480 Mbps) transfer rate, and under the agreement with the USB transfer mode 4, the control mode (control mode), interrupt transfer mode (interrupt mode), volume transmission (bulk mode ), and isochronous transfer mode (isochronous mode).
EZ-USB FX2 series is based on the RAM of the "soft" structure, in the development process to allow unrestricted set and upgraded; It supports full-speed USB bus throughput of the transmission, use the EZ-USB FX2 is designed, you can not end points, the buffer District size and speed restrictions; In addition, the kernel did a lot of secondary instruction, simplify the code, but also accelerated the understanding of the USB features. Based on the above series of EZ-USB FX2 chip features, the development process, using a EZ-USB FX2 series CY7C68013 chip (128 pin), the simplified structure shown in Figure 2.
FX2 can be configured into three different interface modes Ports, GPIF Master and Slave FIFO, the project uses the Slave FIFO mode. In this mode, external logic or an external processor directly connected to the FX2 endpoint FIFO, GPIF is not activated, because the direct control of external logic can be FIFO, so the basic FIFO control signals (signs, chip select, enabling) by the FX2's pin leads. External control can be synchronous or asynchronous, use the internal clock, you can also provide an external interface to the FX2 clock.
2.2 FPGA chip EP1C6-Q240
In this design, the use of the FPGA using Altera's latest CYCLONE chip EP1C6-Q240. It is a high bid of the FPCA chip operating voltage of 1.5V, using 0.13µm process technology, all-copper SRAM process, the memory density of up to 5980 logic cells, contains 20 128 × 36-bit RAM blocks, the total The RAM space to 92,160, embedded phase-locked loop circuit, and a 2 for connection to a specific double data rate SDRAM (deficated data rate) interface. In addition, the chip also supports a variety of I / O standards (including PCI interface, ASSP and ASIC devices can be connected to the interface and the serial device interface, etc.).
Here the role of FPGA and SDRAM in addition to form a large-capacity FIFO, it also requires some control. For this application, HDB3 code to complete the conversion to the NRZ code and the serial and parallel data conversion. Specific problems should be, the user can demand their own FPGA programming.
2.3 A / D converter chip MAX1180
Maxim's MAX1180 is a dual-channel 105Msps, 3.3V operating voltage, low power, high-speed A / D chip, the sampling data to quantify the level of 10. It is the differential input, with a wideband track / hold (track-and-hold) of the dual-channel 9-stage pipeline structure of ADCs, shown in Figure 3. The actual chip includes two icons of the circuit, as the two input channels, without disturbing each other. Separate ways half a clock cycle for each sampled signal through a STAGE, complete conversion to the continuous data output totaling five clock cycles. Each line first by a 1.5-bit flash ADC quantization of input code, and then by the DAC generates a voltage corresponding to the quantitative results for the difference with the input voltage, output voltage, 2 times magnification to the next level after the pipeline processing. A / DD / A two changes and differential treatment aims for error correction to ensure that all stages in the pipeline, ADC offset compensation and no missing codes.
2.4 Hardware Connection
According to the system of data transmission speed and real-time requirements, the interface configuration mode for the work CY7C68013 Slave FIFO mode. When the data acquisition, the hardware connections shown in Figure 4.
A / D converter sampling clock at the same time as the Slave FIFO mode CY7C68013 read and write control the clock, that clock is connected to the interface CY7C68013 IFCLK pin. SCWR / SLRD is CY7C68013 Slave FIFO enable write / read enable signal. Provided to the C7C68013 Slave FIFO FPGA Slave FIFO output enable signal SLOE, only valid data output. FD [15:0] for the 16-bit bidirectional data bus. FIFOADR1: 0 "for the endpoint FIFO selection signal. In the data input is fixed at 00, the choice is the endpoint 2; in the data output is fixed at 10, the choice is the endpoint 6.
3 USB Data Acquisition Software
Software design is essential for the development of a USB device link. USB application software is divided into three parts: the initialization software, host operating system, drivers and customers on the host application. Initialization software is downloaded to the controller firmware code, which respond to a variety of USB standard requests from the system (including the USB device enumeration, the driver choose to load, etc.), to complete the task of connecting the device and the host. Host application software and systems through customer-driven program USBI (USB Device Interface) to communicate, and its main task is to collect the incoming data stream, according to the requirements of processing needed to complete a variety of Windows-based program processing.
3.1 EZ-USB FX2 initialization
Scheduling through the firmware, the host to get the equipment and the completion of the endpoint descriptor data transmission. Firmware programming for the basic structure is as follows:
? initialization, including initialization of the processor and peripheral circuits;
? the main function, including the completion of specific requirements of the code match the device;
? interrupt handling, including handling various interrupt code.
In general, the preparation of the firmware program in two ways. One is familiar with 8051 assembly language for the user, it can be directly written in assembly language, compact structure, high efficiency firmware code; Second, EZ-USB firmware to take advantage of ready-made framework for the function, according to the needs of equipment celebrated added users to accomplish a specific purpose.
USB interface to speed up the development process, the use of EZ-USB FX2 provides some of the framework functions to simplify user code, use the appropriate port (port 2 input port 6 output) using the EZ-USB FX2 Slave FIFO structure using the processing and transmission, the basic firmware application framework functions as follows:
void TD_Init (void) / / This function is used to complete the initial EZ-USB FX2
{CPUCS = 0x10; / / 48MHz operating frequency
IFCONFIG = 0xC3; / / determine operating mode FX2 (slave FIFO) and related settings
IN07VAL = bmEP2;
OUT07VAL = bmEP6; / / enable endpoint 2 input and 6 output endpoint
...
EP2FIFOCFG = 0x6D; / / AUTOOUT = 0, AUTOIN = 1, WORDWIDE = 1
SYNCODELAY;
EP6FIFOCFG = 0x75; / / AUTOOUT = 1, AUTOIN = 0, WORDWIDE = 1
SYNCDELAY; / / 2 and end-to-end configuration of 6, WORDWIDE = 1 configuration is to use 16-bit data lines.
EP2CFG = 0xEA; / / Endpoint 2: input, bulk transfer, the maximum 1024 byte packet, double buffered
SYNCDELAY;
EP6CFG = 0xAA; / / Endpoint 6: output, bulk transfer, the maximum 1024 byte packet, double buffered
SYNCDELAY;
}
void TD_Poll (void) / / This function runs when the device is called repeatedly, it includes a function of user tasks to complete
{
}
BOOL TD_Suspend (void) / / This function is called before the device suspend state
{
return (TRUE);
}
BOOL TD_Resume (void) / / called after the device restarts
{
return (TRUE);
}
Throughout the firmware program, EZ-USB FX2 device is powered on or reset, first initialize all internal state variables, then call TD_Init () function, and the open break, then continue to test firmware control port 0 is received to the SETUP packet. Once received, the firmware to start calling user function TD_Poll (), which features the user code needs to be done in the TD_Poll () function is one. Call is completed, repeat the test port 0 SETUP packet is received, if any, continue to perform device request, call TD_Poll () function; Otherwise, testing whether there is USB USB suspend nuclear incident, if so, call TD_Suspend () function, which return true, if nuclear testing resumed USB event, no, the device into a suspended state, on the contrary, call TD_Resume (), for the next cycle; when TD_Suspend () function returns false, directly to the next cycle.
In addition, the firmware program framework also defines a number of interrupt handler, when used in the corresponding nine can add your own code written, so that is clear and easy to understand, users can not change the whole premise of the program, simply by change the appropriate module, to achieve their function.
3.2 Host Software section
Section includes USB host software drivers owners and local client application. USB client driver program is a standard plug and play support WDM driver, it is to achieve control transfer, interrupt transfer and batch transfer function provides a standard interface. The role of the host application is interacting with the operating system, when the operating system that the new device is connected, it will automatically call the appropriate device driver support for. Coupled with the software requires a graphical user interface to control the use of the function, where the use of VC + + to compile the application, the use of CreateFile get USB handle, use DeviceIoControl to the device driver sends a request to complete the EZ-USB FX2 data batch transfer read and write. Instances as follows:
HANDLE DeviceHandle;
DeviceHandle = CreateFile (\ \. \ Ezusb0, GENERIC_WRITE,
FILE_SHARE_WRITE, NULL, OPEN_EXISTING, 0, NULL);
/ / Get a handle device ezusb0
DeviceIoControl (DeviceHandle,
IOCTL_EZUSB_BULK_WRITE,
LPVOID lpInBuffer, / /; input data memory address pointer
Sizeof (BULK_TRANSFER_CONTROL),
LPVOID lpOutBuffer, / / output data memory address pointer
DWORD nOutBufferSize, / / output buffer size
LPDWORD lpBytesReturned, / / counter variable to receive output data byte pointer
NULL);
/ / Write data to the EZ-USB FX2 device
DeviceIoControl (DeviceHandle, IOCTL_EZUSB_BULK_READ,
LPVOID lpInBuffer, / / input data memory address to
Sizeof (BULK_TRANSFER_CONTROL),
LPVOID lpOutBuffer, / / output data memory addresses approval sunset
DWORD nOutBufferSize, / / output buffer size
LPDWORD lpBytesReturned, / / counter variable to receive output data byte pointer
NULL);
/ / From the EZ-USBFX2 devices read data
ColseHandle (DeviceHandle); / / close the USB handle
Conclusion
The purpose of this project is to signal processing circuit output signal (I, Q two-way), through analog-digital conversion, to meet the 10Mbps transfer rate basis, through the USB interface to complete the data onto your hard work. Proved, based on the USB2.0 high speed data acquisition interface card fully meet the design requirements. It can be predicted, based on the USB2.0 interface, high speed data acquisition card there will be a broad application space.