Abstract: The composition of the wireless transmitter chip TRF4900 wireless digital transmitter circuit, operating in 868 MHz band in Europe and North America 915 MHzISM band, FSK modulation, transmit power 7 dBm, supply voltage 2.2 ~ 3.6 V, through a serial interface to microcontrollers parameter setting and launch control to achieve. This paper introduces the application circuit, the circuit connected with the micro-controller and the parameters settings.
Keywords: wireless digital FSK transmitter
A wireless digital transmission circuit
Wireless digital transmitter circuit wireless transmitter chip TRF4900. TI TRF4900 is produced, monolithically integrated, low cost, can provide a fully functional multi-channel FSK transmitter. Chip can meet the 868 MHz band in Europe and North America, 915 MHz ISM band linear (FM) or digital (FSK) transmitter applications. Monolithic transmitter chip operating voltage 2.2 ~ 3.6 V, typical transmit power is 7 dBm, and has low power consumption. 24-bit direct digital synthesizer 11 of DAC, there are about 230 Hz synthesizer channel space to allow narrowband and broadband applications. Two fully programmable mode - Mode 0 and Mode 1, allows very fast in the two pre-programmed to switch between the settings (such as transmission frequency transmission frequency 0 or 1). Chip integrated voltage-controlled oscillator (VCO), phase-locked loop (PLL) and the reference oscillator, requires only minimal external components to form a complete transmitter. TRF4900 via the serial interface to connect to the TI MSP430 microcontroller. Each transmitter function block can be programmed via the serial interface to its functions. TRF4900 application circuit shown in Figure 1.

Figure 1 TRF4900 Application Circuit Click to enlarge

2 connection with a microcontroller circuit

TRF4900 via the serial interface to TI's MSP430 microcontroller, as shown in Figure 2.
TRF4900 Pin 23 (LOCKDET), PLL lock detect output is high effective. When LOCKDET = 1 时, PLL locked. Pin 11 (MODE), mode selection input, the device in Mode 0 and Mode 1 features a serial control interface through the A, B, C, D word programming. Pin 12 (), sleep control, active low. When = 0, the control register content is still valid, can be programmed via the serial control interface. Pin 14 (TX-DATA), digital modulation input, for the carrier FSK / FM modulation, high effective.

Serial control interface is a 3-wire unidirectional serial bus (CLOCK serial interface clock signal, DATA serial interface data signals, STROBE serial interface strobe), for programming TRF4900. The interface internal registers contain all user programmable variables including the DDS frequency settings, including all control registers. Serial interface timing shown in Figure 3.
The rising edge of each CLOCK signal, DATA pin on the end of 24-bit logical value is written to the shift register. Set STROBE terminal high, programming information is loaded into the selected latch. When the STROBE signal is high, DATA and CLOCK lines must be low. Therefore, STROBE and CLOCK signals are not synchronized. Serial interface can be programmed in the effective work of state or sleep state (standby mode).

Serial interface timing diagram in Figure 3 Click to enlarge
3 TRF4900 settings
TRF4900 direct digital synthesizer DDS is based on the way to generate sine wave with a digital signal. DDS from the accumulator, sine lookup table, digital / analog converter, low pass filter. All digital blocks from the reference oscillator clock. DDS using an N-bit adder counting from 0 to 2N, according to the data in the frequency register ladder wave digital conversion specifications have to construct an analog sine wave. N-bit counter output register of each number, is used to select the corresponding sine wave sine wave lookup table value output. In the D / A conversion, low pass filter to suppress unwanted spurious responses. Analog output signal can be used as a PLL reference input signal. PLL circuit system according to a predetermined reference frequency multiplied several times.
Reference oscillator frequency fref is the DDS sample frequency, but also determine the maximum DDS output frequency, and the accumulator with the number of bits, can calculate the DDS frequency resolution. TRF4900 the minimum frequency step size can be calculated as:
Δf = N × (fref / 2 24)
24-bit accumulator through two 22-bit frequency setting register programming (A word to determine the frequency of mode 0, B word to determine the frequency of mode 1), while the two MSB bits register is set to 0. Therefore, DDS system right down to the maximum bit 1 / 8, as shown in Figure 4.
This bit right and VCO output frequency (fref / 8) × N compatible. MODE terminal based on the logic level, the internal select logic loads DDS-0 or DDS-1 frequency to the frequency register. VCO output frequency fout is set by the DDS-x frequency determined (DSS-0 in the A word, DDS-1 in the B word), VCO output frequency fout is calculated as follows:
fout = DDS_x × N × (fref / 2 24) = N × [(fref × DDS_x) / 2 24]
If you select the FSK modulation (MM = 0, C word, 16-bit), the 8-bit FSK deviation register can be used to program the 2-FSK modulation deviation. 8-bit offset register in the 24-bit DDS frequency register, LSB is set to 0, with a total of FSK offset by the following formula:
Δf2-FSK = N × [(DEV × fref) / 2 22]
Therefore ,2-FSK frequency from the TX-DATA on the level set is calculated as follows:
fout1: TX_DATA = low = N × [(fref × DDS_x) / 2 24]
fout2: TX_DATA = High = N × [fref × (DDS_x +4 × DEV)] / 2 24

The FM output signal of PLL circuit is used as a reference input signal. 2-FSK modulation of the channel width (offset) and channel spacing are software programmable. Minimum channel width and minimum channel spacing depend on the frequency RF system design, the center frequency fcenter = (fout1 + fout2) / 2. When the FSK transmitter, the center frequency fcenter is considered to be an effective carrier frequency.
PLL by the phase detector (PD), frequency detector (PD), charge pump, VCO, loop filter and the external feedback loop in a programmable prescaler (N divider) component. When using an external VCO when, x-VCO-bit will be set to 0. Divider is programmable, frequency division factor N can be set by the C 256 or 512 words.
Power amplifier (PA) to the D word in the P0 and P1 both in programming and provide variable output power level.

Figure 5 Serial Control Word Format
TRF4900 the control word is 24 bits. The first one to introduce is the most significant bit position (MSB), completion of the TRF4900 programming; four 24-bit word must be set, that must be set to A, B, C, D word. Figure 5 shows the definition of the 4 control words. Table 1, Table 2 and Table 3 describes the function of each parameter, Table 4 in the FSK mode, the transmission frequency.
Table 1 Mode 0 Control Register Description
Description of the location of the sign bit plus the median internal settings after the power
Default default
0-PA [10-9] 2 power amplifier mode
P1 P0
0 0 = failure
01 = Attenuation 10dB, enabled through the TX-DATA modulation
1 0 = attenuation 20dB, enabled through the TX-DATA modulation
11 = Attenuation 0dB, enabled through the TX-DATA modulation failure 00b
0-VCO [11] 1 during operation, the pin end will always be enabled (1 = enabled), unless the failure to use external VCO 0b
0-PLL [12] 1 to enable PLL, 1 = enabled, 0 = invalid failure 0b
Table 2 Mode Control Register 1 Description
Description of the location of the sign bit plus the median internal settings after the power
Default default
1-PA [10-9] 2 power amplifier mode
P1 P0
0 0 = failure
01 = Attenuation 10dB, enabled through the TX-DATA modulation
1 0 = attenuation 20dB, enabled through the TX-DATA modulation
11 = Attenuation 0dB, enabled through the TX-DATA modulation failure 00b
1-VCO [11] 1 during operation, the pin end will always be enabled (1 = enabled), unless the failure to use an external VCO 0b
1-PLL [12] 1 to enable PLL, 1 = enabled, 0 = invalid failure 0b
Table 3 describes the supplementary control register
Digit symbol bit position word description of the internal settings after the power increase
Default default
DDS-0A word [21-0] 22 mode 0DDS frequency are all set to 0 0
DDS-1B word [21-0] 22 mode 1DDS frequency are all set to 0 0
DEVD word [20-13] 8FSK all sub frequency register 0 of 0
APLLC word [20-18] to capture the frequency of the acceleration factor 3
A2 A1 A0
0 0 0 = 1
0 0 1 = 20
0 1 1 = 60
1 1 1 = 1400000b
NPLLC word [17] 1PLL frequency points
0 = 256
1 = 5122560b
MMC word [16] a modulation mode selection. To set the FSK data input
TC-DATA-pin terminal behavior.
0 = FSK / FM
1 = do not use FSK mode 0b
Table 4 in the FSK mode of firing frequency (MM bit set to 0)
Pin terminal transmission frequency
STDBYMODETX-DATA
100fout = fref × N × (DDS_0) / 2 24
101fout = fref × N × (DDS_0 +4 × DEV) / 2 24
110fout = fref × N × (DDS_1) / 2 24
111fout = fref × N × (DDS_1 +4 × dev) / 2 24
Conclusion
Formed by the TRF4900 and MSP430 wireless digital transmission circuit can be easily embedded in a variety of measurement and control systems; in the instrumentation data acquisition systems, wireless meter reading systems, wireless data communication systems, computer systems, remote telemetry application.