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Write Cycle Timing Diagram for Minimum Mode

  • The working of the minimum mode configuration system can be better described in terms of the timing diagrams rather than qualitatively describing the operations.
  • The opcode fetch and read cycles are similar. Hence the timing diagram can be categorized in two parts, the first is the timing diagram for read cycle and the second is the timing diagram for write cycle.
  • The read cycle begins in T1 with the assertion of address latch enable (ALE) signal and also M / IO signal. During the negative going edge of this signal, the valid address is latched on the local bus.
  • The BHE and A0 signals address low, high or both bytes. From T1 to T4 , the M/IO signal indicates a memory or I/O operation.
  • At T2, the address is removed from the local bus and is sent to the output. The bus is then tristated. The read (RD) control signal is also activated in T2.
  • The read (RD) signal causes the address device to enable its data bus drivers. After RD goes low, the valid data is available on the data bus.

  • The addressed device will drive the READY line high. When the processor returns the read signal to high level, the addressed device will again tristate its bus drivers.
  • A write cycle also begins with the assertion of ALE and the emission of the address. The M/IO signal is again asserted to indicate a memory or I/O operation. In T2, after sending the address in T1, the processor sends the data to be written to the addressed location.
  • The data remains on the bus until middle of T4 state. The WR becomes active at the beginning of T2 (unlike RD is somewhat delayed in T2 to provide time for floating).
  • The BHE and A0 signals are used to select the proper byte or bytes of memory or I/O word to be read or write.
  • The M/IO, RD and WR signals indicate the type of data transfer as specified in table below.